dag1

Members
  • Content Count

    9
  • Joined

  • Last visited

About dag1

  • Rank
    Newbie

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. I am using the Basys3 version C. I am trying to learn to use Vivado's Integrated Logic Analyzer (ILA). But I keep getting a message as if the clock source is not seen by the ILA. I tried to get assistance with this issue on the Xilinx forum, but so far we haven't been able to make progress on resolving this issue. Here is a link to that: https://forums.xilinx.com/t5/Design-Tools-Others/Message-No-debug-cores-when-trying-to-use-ILA/m-p/936602#M13274 I was wandering, being that this here is Digilent forum, perhaps someone has been successful in using the ILA on Basys3 ?
  2. I found on Digilent site the .xdc file for Basys3 Rev. B. I need the.xdc file for Rev. C. Where is it?
  3. Can you please list here all the boards that work with Vivado ? (preferably in increasing price)
  4. I have Atlys board, and it has 2x6 Pmod input I need a 7-segment for it, but I only saw a Pmod 7-segment which is based on one row of pins (the 2x6 is two rows of 6 pins) Can you suggest for me such a 7-sement Pmod for 2x6 , maybe another manufacturer?
  5. dag1

    ISE and Atlys on Linux

    I found the mistake I chose LX45T instead of LX45 in the ISE So now choosing LX45 solved the problem
  6. dag1

    ISE and Atlys on Linux

    I am trying to program the Atlys card from the ISE on Linux I installed ISE and Digilet Atlys .tar files. and plugin file I create a project in ISE The Atlys board is not on the list, so I choose the FPGA type directly, XC6SLX45 CSG324C Then in Pre-Synthesis, which I create the UCF file, I use the FPGA (PlanAhead) I choose Site for every of the signals, (FPGA pins) However, some of pin codes on the Atlys board, for instance the Slide Switch D14, does not appear as a valid \FPGA pin in the PlanAhead. Who is right? the PlanAhead or the codes specified on the board itself? Please advise thanks
  7. The thing is that with Windows 10 and ISE one is running on a virtual Linux machine (comes with the ISE installation). So not sure which ins I should be installed, for the Windows or for Linux ? I tried for Windows, installed Adept 2. I can see the Atlys card connected and I can run the tests that Adept provides But this does not solve the problem, when I run iMPACT in ISE I get the Cable error. Do you know how to install the Linux version of the plugins and drivers? Is there any guide on installing whatever is necessary for Atlys card on Linux? I could try to install them in the Virtual Linux box that ISE came with
  8. I tried your suggestion , so I skipped setting the board, and set the FPGA directly in the Project settings I managed to do Presynthesis, generated UCF file, did Synthesis, but when I run iMPACT to program the FPGA on the Atlys I get the following error: GUI --- Auto connect to cable... INFO:iMPACT - Digilent Plugin: Plugin Version: 2.5.2 INFO:iMPACT - Digilent Plugin: no JTAG device was found. AutoDetecting cable. Please wait. *** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz regardless of explicit arguments supplied for setting the baud rates PROGRESS_START - Starting Operation. Connecting to cable (Usb Port - USB21). Checking cable driver. File version of /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030. File version of /usr/share/xusbdfwu.hex = 1030. Using libusb. Kernel release = 2.6.32-358.el6.x86_64. Cable connection failed. Connecting to cable (Parallel Port - parport0). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport1). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport2). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport3). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. PROGRESS_END - End Operation. Elapsed time = 1 sec. Cable autodetection failed. WARNING:iMPACT:923 - Can not find cable, check cable setup ! Any advise?
  9. As is well known Xilinx latest version of ISE supports Windows 10 in a limited way so that old Spartan 6 FPGA can be used. this ISE version is called: Xilinx_ISE_S6_Win10_14.7_ISE_VMs_1211_1 Apparently, they only have the Spartan 6 Starter Board, but not the Atlys board (although Atlys is based on the Spartan 6). Can anyone in Digilent provide me with the necessary files that would make the ISE recognize the ATLYS card? thanks