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zygot

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Topics posted by zygot

  1.  

    ADP2230

    By zygot, in Suggestions & Feedback

    • 0 replies
    • 57 views
  2.  

    Is the RPi5 suitable for paring with an FPGA?

    By zygot, in Technical Based Off-Topic Discussions

      
    • 0 replies
    • 533 views
  3.  

    Forum Guilelines

    By zygot, in Suggestions & Feedback

    • 1 reply
    • 2,913 views
  4.  

    Question: NetFPGA_1G_CML QDRII+ IOSTANDARD isn't supported by VIvado MIG

    By zygot, in FPGA

    • Awaiting best answer
    • 0 votes
    • 0 answers
  5.  

    HDL topics

    By zygot, in Technical Based Off-Topic Discussions

      
    • 13 replies
    • 1,215 views
  6.  

    Why does Digilent like to irritate their customers?

    By zygot, in Suggestions & Feedback

    • 9 replies
    • 548 views
  7.  

    Using DDR as a Video Frame Buffer

    By zygot, in Tutorials

      
    • 13 replies
    • 3,027 views
  8.  

    Question: Time to ditch Windows for AMD/Xilinx FPGA Development?

    By zygot, in FPGA

    • Awaiting best answer
    • 0 votes
    • 2 answers
  9.  

    Question: Waveforms on the Eclypse-Z7

    By zygot, in Test and Measurement

    • Awaiting best answer
    • 0 votes
    • 1 answer
  10.  

    Debugging with the FTxxxx Mini-Modules

    By zygot, in Tutorials

      
    • 0 replies
    • 556 views
  11.  

    Question: Digilent 128x32 OLED Display IP doesn't work properly

    By zygot, in FPGA

    • Awaiting best answer
      
    • 1 vote
    • 22 answers
  12.  

    Does the Future of Programmable Logic include You?

    By zygot, in Off Topic

    • 7 replies
    • 6,155 views
  13.  

    Question: Vivado issues work assignments ... again. New chores for 2020

    By zygot, in FPGA

    • Awaiting best answer
      
    • 0 votes
    • 1 answer
  14.  

    Manipulate PL logic using PS registers

    By zygot, in Tutorials

      
    • 0 replies
    • 1,177 views
  15.  

    Question: Digilent master constraints format change request

    By zygot, in FPGA

    • Awaiting best answer
    • 0 votes
    • 0 answers
  16.  

    A Guide to Using DDR in the all HDL Design Flow 1 2

    By zygot, in Tutorials

      
    • 35 replies
    • 8,474 views
  17.  

    Question: NetFPGA-1G-CML QDRII+ interface

    By zygot, in FPGA

    • Awaiting best answer
    • 0 votes
    • 8 answers
  18.  

    Question: NetFPGA-1G-CML

    By zygot, in FPGA

    • Awaiting best answer
    • 0 votes
    • 6 answers
  19.  

    The Current State of FPGA tools

    By zygot, in Off Topic

    • 1 reply
    • 1,219 views
  20.  

    Boost your Memory

    By zygot, in Project Vault

      
    • 0 replies
    • 901 views
  21.  

    Better than a ZYNQ UltraScale+ ?

    By zygot, in Technical Based Off-Topic Discussions

    • 3 replies
    • 2,027 views
  22.  

    Genesys ZU-5EV

    By zygot, in Sales Questions

    • 10 replies
    • 2,060 views
  23.  

    Digilent's Forum Website is Problematic

    By zygot, in Suggestions & Feedback

    • 4 replies
    • 1,140 views
  24.  

    Inter-board Data Transfer Project

    By zygot, in Project Vault

      
    • 8 replies
    • 1,901 views
  25.  

    Question: Trouble posting material

    By zygot, in Other

    • Awaiting best answer
    • 0 votes
    • 0 answers
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