zygot

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Everything posted by zygot

  1. Do not try an drive a motor winding with a device IO pin that is not conditioned for such duty. Reactive loads will do nasty things to your device and subject it to conditions well outside its specified operation range. Your output pin must be isolated by a proper driver circuit.
  2. I forgot to mention the MAX11254 EVM. If you need a high resolution multi-channel delta-sigma ADC for low frequency applications this board is very usable. It was designed to be used in a stand alone mode via a USB interface or with the Zedboard; so it should work with either the Nexys Video or Genesys2 boards as well. There are a lot of options for using your own input signals. It has 50 or so jumpers to locate, which makes it flexible, but may make you cross-eyed for a few days trying to locate all of them. There just aren't that many pins in the FMC interface to trace through which is nice.
  3. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the featured device very very carefully to make sure that it can do what you want it to do. This is not nearly as simple as you would think, especially for ADC devices where specmanship, little white ( sometimes closer to black ) lies, and covering up 'features' that might render the device useless for your requirements has always been the rules of the road. Pore over the schematic for the EMV and trace every pin through the connector to ensure compatibility with your FPGA board. Pay particular attention to power supply pins. Download the supporting software, when available, and understand what you get or don't. Understand that good ADC interfaces, on the analog side, tend to be very application specific. The ADC demo boards tend to be general purpose; but not always. Not listed below is the ADS4449 EVM that I managed to get working with the KC705 board a number of years ago. This 4 channel high speed ADC EVM is set up for narrowband processing of signals centered around 185 MHz. It served it's purpose but I can't recommend it. HSMC compatible boards. ADC/DAC Linear Technology DC2459A LTC1668 16-bit 50 Msps DAC This is one of those rare EVMs designed to connect to an FPGA development board. It can connect directly to a board with an HSMC connector, a DE0 Nano, a Mimas or Mojo board. Mine is always attached to a DE0 Nano and ready to go. I use an external TTL USB UART for control. The DE0 Nano is a cheap and very handy board to have around. ( If only it had a nice Artix FPGA... not that I have anything against the Cyclone V ) Linear Technology DC2390A for LTC2500-32. 2 LTC2500-32 32-bit ADCs and 2 LTC1668 16-bit 50 Msps DACs Connects to any FPGA board with an HSMC connector. The EVM is intended to be used with the Cyclone V SoCkit and has slick software support if used with this ARM based board. I prefer rolling my own interface and using another FPGA platform. Interesting approach o the software side. Terasic makes a couple of not too expensive ADC/DAC HSMC compatible add-on boards. I've already posted a description of a demo project that I completed ( well as far as I need to for now ) recently showing one way to use the Ethernet PHY to make use of such boards. In recent years I've really lost my enthusiasm for low end Intel FPGAs and Quartus tools so that post isn't as silly as you might assume that it is. USB 3.0 Both FTDI and Cypress offer reasonably priced development kit options for using their USB 3.0 interface devices for both HSMC and FMC connector equipped boards. In fact for the FMC versions these are among the only inexpensive mezzanine boards that you will find. I much prefer the flexibility of the Cypress FX3 but be aware that you need to do some embedded ARM development and there's a steep learning curve. If you want to learn about USB this is the way to go. FMC compatible boards. The FMC ecosystem is, with few exceptions, a very expensive place to play in. However on rare occasions you can get lucky. Understand that none of the boards below were intended to connect directly to an FPGA development board. Analog Devices EVAL-AD7761FMCZ AD771 8-channel 16-bit Simultaneous Sampling ADC. I've used this board with the Nexys Video with minimum effort. This is one of those devices where you can be very disappointed if you don't completely understand everything in the data sheet. Analog Devices EVAL-AD7616SDZ AD7616 16-Channel DAS Dual Simultaneous Sampling ADC. This board requires a SDP-I-FMC interposer. I didn't complete a project using it but haven't run into any obstacles hardware-wise. This is another device that requires very careful scrutiny before deciding that you want to spend your time or money on it. ** This advice also applies to FPGA boards that you are thinking of purchasing. If you want to use a particular feature, say DDR, find out if the vendor offers a usable demo showing how you might use it for your project. Find out if you need an evaluation license to build the demo for yourself in order to use that feature. There's only one way to do this... Before making a purchase install Vivado or ISE and see if you can actually build the demo projects for a board. Support, support, support. So what kind of support is provided for the board that you are interested in? Digilent is all over the place here. A very few boards have demo projects with HDL sources. One such board is the Nexys 7-A100T (Nexys 4 DDR) that has an OOB with VHDL sources for most of it's features. It does have a few IP .xco files that are supposed to work with Vivado 2018.2. I was unable to use the sources to generate a bitstream using Vivado 2018.2 SP1. ( I don't have the board so I didn't spend a lot of time trying only because I wanted to look at the DDR IP to reply to a posted question regarding DDR performance. Companies can pretend to offer more support than they really do by offering board design Xilinx IP flow demos. I personally, want to see HDL source as a measure of commitment to a product. Even though Digilent has shown that it's possible; it's hard to mess up an HDL demo. If there's very little in the way of providing build-able demo projects for board features or it take years to provide a reasonably accurate User's Manual these are big red flags. It doesn't mean that the board is useless, just that you had better have the experience and skill, and most importantly for me the time to write your own interfaces Tips for beginners. Not everything that board or even IC vendor makes is wonderful. If they spent money developing a product then they sure will try to find a customer to pay for those development costs. Sometimes, the only way to identify the dirty little secrets is to observe what's missing in a data sheet or sales blurb. If a normal feature is usually highlighted for most similar products and noticeably absent for the one that you are eyeing then this is a big red flag. What's missing is sometimes more informative than what's stated.
  4. I use the ATLYS Ethernet PHY all the time but I confess that I've never tried using it in 10/100 Mbsp operation. The Marvel 88E1111 is ubiquitous and unfortunately requires an NDA to read documentation about how to program it. Your problems could be related to register settings or perhaps failed timing paths. You don't mention a timing score for your routed design. This is where your debugging skills need to serve you. I'd start with a couple of debug ILAs ( one for 125 MHz and one for 25 MHz ) operation to try and figure out if the clock switching logic is failing. As you know the 88E1111 comes out of reset with its registers set to various modes depending on the state of a number of output pins. This information is freely available in the device data brief from Marvel. Are you resetting the PHY after switching from 1 G to 10/100? Have you tried putting the PHY into 10/100 before connecting to the switch? During debug I'd try to reduce the number of variables to a minimum. I'd start without using the switch and connect to a device with a known good 10/100 Ethernet port. It may take a while and some effort but you will figure this out.
  5. zygot

    Nexys A7 Reference Manual: SDRAM - Mbps vs MBps

    The convention for external memory data rate is on a per pin basis so the reference manual is correct. The peak data rate out of the external memory, as you surmise, depends on the width of the physical memory. If you have a single port (channel) external memory controller then a more important metric is how many bytes/s can you get out of the controller into your FPGA design. If you have a multi port controller vying for access to the memory then the peak data rate out of the external memory becomes significant. There are a lot of moving parts to trying to figure out if an external memory implementation will support any particular application as you likely suspect. There are a lot of factors to consider such as maximum DDR data rates for a particular device, memory burst length, and controller verses data clock ratio. [edit] I should also point out another possible source of confusion. Clearly the 650 Mbps refers to 'million bit per second'. Once you start talking about 'mega bytes per second' you'd be referring to million bytes per second divided by 1.048576. The hard disk drive manufacturers have been pulling our legs for some time by redefining the term megabyte to enhance the perceived capacity of it's products.
  6. zygot

    Prototype for thesis - tarjet selection, help!

    My first impulse would be to investigate a uC software solution for such a project; especially if your FPGA development experience is limited. I love solving problems with an FPGA but it isn't always the most sensible way to go. There are a number of inexpensive boards like the Raspberry Pi an adding a cheap interface of your own design could be fairly easy. Texas Instruments offers some cheap Piccolo DSP development boards and a nice software development platform. Keep It SSimple... or perhaps I should say keep the demonstration development as simple as possible so that you have the time to concentrate on making the demonstration as impressive as possible. [edit] If you have the skill and just want to do an FPGA based platform the CMOD can be easily be connected to a breadboard or custom PCB interface (Express PCB is one that I have experience with) supporting connection interfaces to all of the sensors and actuators that you need. Despite its deficiencies I still use my CMOD-A7 modules and just work around the issues. There are other inexpensive FPGA boards with a lot of IO as an alternative.
  7. @Matthew Cabral I guess that you didn't read my post about EVM/FPGA development board experiences. It just so happens that I did manage to cobble together a connection between the ADS4449 EVM and a KC705, so in theory you should be able to make it work with the Genesys2. I had to use a separate intermediary adapter between the EVM and the FMC connector. The EVM had support studs that I had to remove. The whole thing didn't end up being very mechanically sound. I had to supply additional supply voltages to the EVM. To repeat warnings that I've posted before , you have to understand all of the documentation carefully before making a purchase. The ADS4449 EVM is set up for narrowband (125 MHz) operation for signals centered around 185 MHz. In theory you can change components to change this. The data interface is simple enough but you need to implement a serial interface to set up the ADC. I just used the on board USB interface so that I could use the Ti software to set up the chip. You'll want to put the ADC into test data modes to verify the FPGA interface design. This board is a good example of surprises waiting the unsuspecting or knowledgeable user. I managed to do what I needed but can't recommend it to anyone. It was a lot of tedious work. Most high speed ADC evaluation board require a special baseboard which usually has an FGPA and accompanying software support. These things are usually geared to allow testing the performance of the device, not for use in a particular application. There just isn't many options for 4-channel high speed ADC equipped FPGA boards in a reasonable price range. One possibility for you might be: Cyclone V GT Development board ( 2 HSMC connectors ) 2 Terasic DDC boards ( each with 2 14-bit 150 MHz ADC and 2 14-bit 250 MHz DAC devices ) There are more ADC options in the Intel (Altera) world and Terasic makes a number of boards with multiple HSMC connectors. I have used the Cyclone V GT board with a DDC so I can confirm that they work together. You don't need such sample rates and in theory you could use one ADC to sample 4 channels sequentially.. if you understand the ramifications. On last warning. Asking what people think about possible compatibility of products is a good way to get into trouble. It's pretty easy to be well intentioned and provide bad advise or advise that's easy to misinterpret. Unless someone has actually had success with particular boards they can't offer useful guidance. [edit] Since I mentioned the Cyclone V GT development board I should add a warning to anyone deciding to purchase one. Some idiot placed SMT devices very close to the HSMC mounting post holes. The first time I connected a board to one of these connectors I sheared off on the these SMT ICs (part of the board JTAG chain) and had to wire around it in order to configure the board.... not a way you want to discover board features. For the record it's a very good and useful Cyclone V board...
  8. zygot

    Adept software Manual ... looking for author

    @Pavel_47 , I have no experience doing what you intend to do but I suggest trying the Xilinx community forums. Intel also has a similar venue. I figure that having access to the largest set of eyes is the best chance of connecting with someone who has helpful information.
  9. zygot

    Adept SDK C# Library

    In case anyone is unaware of this. DEPP is relevant to the older Digilent boards ( ATLYS, GENESYS) using the Cypress FX2 USB endpoint solution for asynchronous communication. All of their newer boards use (sigh!!!) FTDI USB endpoint devices. I suspect that the posted DLL is of little use to very many people.
  10. zygot

    Adept SDK C# Library

    Except for those posting here.... but one thing common to all who off advice, at any price, is that their efforts are likely to result in resentment rather than gratitude.... Unless it's on a scam topic... CMM Anyone?
  11. zygot

    Adept software Manual ... looking for author

    Hi @Pavel_47, I'm afraid that I still don't understand what your goals are. If you are interested in configuring FPGA devices Xilinx device documentation is excellent and there are application notes and a few demonstration projects. If you want to pass data between a configured device and a PC xc6lx45 recently posted a project showing how to do that using the BSCAN primitive. I can't think of other uses for JTAG. Designing a boundary scan system to do say, a complete PCB test, will require a bit more research. There is an open source JTAG effort that might be instructive. IEEE 1149 covers boundary scan.
  12. zygot

    Adept software Manual ... looking for author

    @Pavel_47, I've noticed a few of your recent posts and understand your frustration. Might I suggest that the Adept software isn't the only possible approach to using the USB resources. I've used the FTDI driver APIs with the Nexys Video and there's a very recent project posted to the Project Vault that's an excellent tutorial for doing what you appear to be interested in for the CMOD. Before venturing into specifics related to any USB device or API you have to have to have a good understanding of USB concepts and protocol. There are other resources for that.
  13. zygot

    VHDL: Why are those 2 variants not equivalent?

    Be careful with nested if..then..else statements. This structure implies priority. In ISE you can view the synthesis results in an RTL view to see a schematic of how it interpreted your code. Did you try an simulate the two variants? You haven't found a bug in either ISE or VHDL but figuring this out might be a valuable exercise. In VHDL the ':=' and '<=' assignments are not equivalent
  14. zygot

    busbridge3: High-speed FTDI/FPGA interface

    @xc6lx45, Well, thanks for the support. Again, it's a fantastic tutorial and highly usable. As I mentioned I intend to massage it a bit and perhaps add my own twist to the interface for a future project.
  15. I had intended to include these scope pictures: One shows the DAC waveforms after the first DAC packet updated the waveform buffers. The waveform buffers are initialized in the configuration bitsteam. The other shows the latency from when the ATLAS gets an ADC packet to when a DAC packet is sent.
  16. Connecting Intel (Altera) and Xilinx worlds with a cheap cable. I've been doing FPGA development using Altera and Xilinx development tools for many years now. This has produced a lot of years long itches that I've found hard to make go away. Generally, these irritations are caused by obstacles thrown in my way by vendors wanting get money out me. It's really hard to find inexpensive Altera based development boards with an Ethernet PHY not connected to an ARM PS, or with a decent UART port or any useful USB port. However, you can find ways to connect Altera based development boards to ADC/DAC devices with reasonable performance. In the Xilinx world it's the other way around. Both vendors have made playing with transceivers very difficult, especially for the non-premium devices. Both vendors try to use their soft-processor based development flow as the only way to do anything useful with their development boards. The HSMC has long been the standard IO interface providing a reasonable number of IO for both low speed and high speed uses. But try and find a reasonably priced Xilinx development board with an HSMC connector. For too many years the 8 signal PMOD has been the only IO available in the Xilinx world until recently when boards with an FMC connector have become available. Recently, expensive Altera boards with an FMC connector have also become available. So, I have a lot of hardware that can do a lot of things... except what I want. What to do... what to do... Recently, I released an Ethernet test tool to the Digilent Project Vault. If view counts are any measure there hasn't been much interest. I've recently make a demonstration project that resolves a few of the previously mentioned itches. Below is a brief description. The project connects my ATLYS board to two channels of 100 MHz ADC and DAC interfaces. The ALTYS uses the high speed USB 2.0 Adept interface to connect to a C program for downloading DAC waveforms to and upload ADC samples from the DDR2. DAC waveforms can be of arbitrary length. All of this data goes through the ATLYS Ethernet PHY to an Altera Cyclone V GT based development board with 2 HSMC connectors and the rare Ethernet PHY - FPGA fabric connections. One of the HSMC connectors has a Terasic DDC board with 2 250 MHz DACs and 2 150 MHz ADCs. At best Gigabit Ethernet supports 125 million bytes/s full duplex data rates... but the good news is that this is, unlike USB, a sustainable rate with very low latencies. Currently, the project runs all 4 converters at a 100 MHz sample rate. The sample rates supported through the Ethernet cable are 25 MHz. DAC samples from the ATLYS use 4X interpolating filter in the Cyclone FPGA to create 100 MHz samples. ADC samples are decimated to 25 MHz sampling rates. DAC data is sourced from 2 16 KBx16 block ram DPRAM waveform buffersi a ping-pong arrangement so that I can write new waveform data without disturbing the DAC outputs. Whenever the read pointer crosses from one half of the buffer to the other half the Cyclone sends an ADC packet to the ATLYS with 8192 samples. The start of the packet is used as a synchronizing signal to the ALTYS to know when to send the DAc packet. The Ethernet PHYs transfer 100 million bytes/s for DAc waveforms longer than 16384 samples continuously. That's the overview. Why bother to post this? I'm not the only one with an itch problem. Hopefully, this project will spark some interesting solutions to their problems. I've provided 2 pictures to show what's going on. In both CH1 and CH2 are the DAC outputs. CH3 is the ADC packet and CH4 is the DAC packet. Notice the latency bewteen the packets in the blowup image.
  17. zygot

    busbridge3: High-speed FTDI/FPGA interface

    Yeah, my eyesight isn't that great to spot the parens on my own... the source for my last build (what was the latest source from GIT) was not the updated version. The fixed lines stopped throwing exceptions after I put the rest of the code back to yours to run everything. I did download your latest this morning and installed it into a fresh directory. Built the bitstream and C# application. I don't get any error but am not sure what I am looking at. Your USER2_demo runs twice but doesn't provide any notification of success... so I guess that it passes. The application repeatedly prints out the lines: configured test register delay... round trip time... margin 1: margin 2: the reported round trip times seem to be around 0.260 ms if the CMOD is plugged into a hub and around 0.06ms if I plug the CMOD directly into a PC USB port. The one LED does blink at a 1 sec interval. I never do get to the "All tests pass..." declaration that I'm expecting from the program.cs source. For what it's worth, last night as I was playing around with the SharpDevelop debugger it appeared that the second call to getUInt32 at line 505 in bb3_lvl4_memif.cs was where the exceptions were happening. I'm going to try an see if I can make the CMOD Verilog do something a bit more interesting than blink the LED... Sorry for the troubles...
  18. zygot

    busbridge3: High-speed FTDI/FPGA interface

    The committed lines seem to be there. If I uncomment the memTest32 calls and comment out the try/catch I get the following: System.OverflowException: Arithmetic operation resulted in an overflow. at busbridge3.memIf_cl.getUInt32(Int32 offset) in c:\Projects\busbridge3-master\busBridge3\bb3_lvl4_memIf.cs:line 362 at busbridge3.memIf_cl.getUInt32(Int32 offset, Int32 num) in c:\Projects\busbridge3-master\busBridge3\bb3_lvl4_memIf.cs:line 373 at busbridge3.memIf_cl.memTest32(Int32 memSize, UInt32 baseAddr, Int32 nIter) in c:\Projects\busbridge3-master\busBridge3\bb3_lvl4_memIf.cs:line 505 at Program.Main2(String[] args) in c:\Projects\busbridge3-master\busmasterSw\Program.cs:line 162 at Program.Main(String[] args) in c:\Projects\busbridge3-master\busmasterSw\Program.cs:line 8 I'm running WIn7 64-bit as well.
  19. zygot

    busbridge3: High-speed FTDI/FPGA interface

    There's a problem with your memTest32 function... haven't found out where the overflow is but possibly a cast issue ?
  20. zygot

    busbridge3: High-speed FTDI/FPGA interface

    I created an executable using your sharpDevelop_build directory but got the exact same results as the project that I created. Commenting out the try/catch lines just created an exception in the memif without the graceful termination. I'll try and debug but it may take awhile. I'm running in WIN7 (far far away from the internet )
  21. zygot

    busbridge3: High-speed FTDI/FPGA interface

    @xc6lx45 Hi, I had no issues creating a bitstream in Vivado 2018.2 using your (imported) project file. While trying to recreate your project I ran into a snag with the C# code. I have VS2010 tools so of course your project files and solutions are unusable. I did manage to use the sharpDevelop tool you suggested. The executable configured the board and then threw an unhandled exception... (Arithmetic operation resulted in an overflow) but still terminated gracefully. I'm afraid that my C# skills have become rusty. I had to modify the path for the top.bit since I was running out of a different directory than you did ( I had to create a new solution project); simple enough to resolve. Let me make a few suggestions for such projects: Identify exactly what tools (versions) you use to create components Since Microsoft tools are notorious for not playing nice with other versions of itself you might want to anticipate that most users will have to do a work-around; not a complaint, just a thought. Assume that you audience might have a different development trajectory, especially for PC software, than you did when developing the project. I got too close to quit but so far haven't accomplished a verification that your project can be recreated. I know that you are interested an any feedback, as I am for any projects that I've posted. regards
  22. zygot

    High speed output on PMOD ports

    I hate myself for having to defend any use of those silly differential PMODs but I'll make the following observations: The FMC is a very complicated high density connector designed to connect to a well designed mezzanine card thst's plugged into it. It's NOT a general purpose GPIO connector suitable for breadboarding a signal source to external devices. You likely don't want or need the complexity of doing a ZYNQ based design just to put out a couple of PWMs. I use and like the Zedboard but it's not what you want. There are much cheaper solutions available from Digilent with those (usually $%^!) differential PMODs. It's unfortunate that Digilent can't be bothered to create pdf versions of it's User's Manuals any more so you have to do online comparison of boards. I looked at the Arty A7 board and they don't mention the usual toggling rate verbiage you will find for the description of the high speed PMODs that user's manuals for other boards have... but I doub't that the performance is all that different for your needs. You've done something that I've been unable to do, which is find a use for one of these things. Oh, and no your board doesn't have a high speed PMOD.
  23. zygot

    High speed output on PMOD ports

    In this case you may well be able to use a differential PMOD. Just assign the signals to the _p or _n pins of each differential pair and assign the corresponding opposite polarity pins to GND. You should have no trouble with 100 MHz outputs as long as you pay attention to details in terms of getting the signals to your receiving equipment. You can determine which are which by the FPGA pin names on the schematic. You probably want some form of termination at the receiving end to minimize reflections. In the constraints file you might want to use the lowest appropriate drive strength and slowest appropriate slew rates on the driver. If you cable all 8 PMOD signal pins ( 4 signal and 4 GND ) plus the 2 dedicated GND pins you might be OK. At around 100 MHz and above digital is analog for all practical purposes so this is right up your alley.
  24. zygot

    busbridge3: High-speed FTDI/FPGA interface

    @xc6lx45, After second, more through look, my reaction has gone to really really nice! Excellent work! For anyone wanting a one step PC application to FPGA application this is a fantastic tutorial. [edited] And by the way best wishes in your new endeavour. When you need a change of pace stop by and drop off more of worthwhile your insight. We will all be poorer off without them.
  25. zygot

    High speed output on PMOD ports

    So an adequate answer to your question is a bit complicated. Do you want outputs or inputs? How many outs and ins do you need? Single-ended or differential? What logic standard are you connecting to? The answer to this question is leads to the next one which is what is the termination scheme? Most Digilent PMODs have, for good reasons appropriate to their typical user need, series resistors. This is usually not consistent with ideal transmission line design. If you have the tools to make an FMC mezzanine board interface then that's a possibility. I've done projects with these connectors in my DYI PCB oven. The PCB layout and component footprint wan't easy... the results were good enough for the job at hand but not merchantable. I'd look at small FPGA modules with high density connectors and good support.... I don't have experience with any to make specific suggestions. Look at Opal Kelly, They have a new Artix board with their new SYZYGY ports and a USB 3.0 interface. If you can deal with their niche philosophy this might be good. I have used them in the past. Find my latest post about it in the Technical Based Off-Topic section for more commentary. There's no way to give you a good answer without knowing what you want to do....