zygot

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Everything posted by zygot

  1. I assume that you mean a contiguous stream of ADC data samples. There's not a lot of processing that you are going to do on those samples with a Z7020 ZYNQ on the fly as data is being captured. If you look around on other areas of this site you can see how to capture 128 M samples of 4 ADC channels into DDR memory that can be processed on a PC later, using 2 ZMODs and a non-ZYNQ platform. The Digilent AXI IP isn't high performance or even good at demonstrating what a Z7020 and SYZYGY is capable of and I don't expect to see anything better. Is it possible to use AXI to DMA huge quanti
  2. I love happy resolutions to frustrating problems. Digilent could be more proactively helpful for basic customer issues. Perhaps a FAQ section or topical list of problem resolutions that customers could sift through on the web site? We all know that trying to update all documentation to keep up with problems caused by Xilinx tools version releases isn't feasible. But there has to be a better way, right?
  3. Most of Digilent's FPGA boards use an FTDI USB bridge device that can have 2 or more endpoints, all using one cable. One is used for JTAG and one as a UART. Vivado Hardware Manager communicates through the JTAG endpoint, so COM4 isn't what you are looking for. If you look under Universal Serial Bus Controllers in Deevice Manager you should see a USB Serial Converter show up when you plug in a cable attached to your board. The CMOD-A7 uses the same cable for programming and UART communications so a COMxx device will also show up. So how do you know what device goes with your cable? Look at
  4. Let's see if we can solve this. What OS is Vivado running on? Have you queried the OS tools to see if any USB devices get enumerated when you plug in the USB cables ( and for the Basys3 have the board powered on? ). For Windows this would be Device Manager ( usbview.exe is more helpful ) and for Linux it would be : dmesg | grep usb lsusb lsusb has command line options for more verbose replies. Vivado 2019.2 isn't the best version to use as it was the first time Xilinx abandoned the SDK tools and forced everyone to use Vitis. I still use Vivado 2019.1 for normal FPGA de
  5. I'm not exactly sure what you mean by 'program the port'. If you want to setup the internal DAC or ADC registers on one of the ZMOD pods you can use the low level controller(s) VHDL code that Digilent supplies in the vivado-library repo. These setup your ZMODs to function after power-on. You'll need some way to write registers in your HDL code if you want to change the default settings post configuration. You can use the USB DPTI for this, or you can add a UART interface to do this. If the preceding information isn't what you are looking for you'll have to be a bit more expansive in
  6. Why do you think that a soft processor ( or Vitis for that matter ) is necessary for your project? If you don't use MicroBlaze you don't need to use either the board design flow or any software development tools like Vitis. Your board is perfectly suited to an all HDL design flow. Just create a new project in Vivado and add all of your HDL source code, plus your constraints file(s). You can still use Vivado IP for clocking, internal storage etc. if that's convenient. FPGAs just aren't well suited for implementing replacements for general purpose computers systems. ( an exception mig
  7. Better yet, to get started, ditch the MicroBlaze and board design system altogether. Everything will be simpler. No mysterious signals added to your intended design. No hardware to export to the software development tools. No software co-design co-debugging. A good rule in engineering is to avoid doing things that make your work complicated and difficult. If you find yourself working for the tools, you're living in an unhappy universe. Make the tools work for you. The tools can't create designs, so don't allow them to dictate to you how you can do the design work.
  8. I've not used the USB104A7 nor do I use soft processors. I do use wrappers when targeting a ZYNQ device and using the board design flow to develop a basic ZYNQ system. After verifying and generating the board design I have Vivado create a wrapper file in VHDL or Verilog for the system. I make sure to uncheck the default setting when doing this and tell Vivado that I, not Vivado, will be managing the wrapper HDL. My top level entity instantiates the system wrapper as a module/component along with all of the other modules/components in the design. For ZYNQ designs the toplevel entity
  9. Wow, that sounds dangerous. FT_PROG is a utility for changing the configuration values of the EEPROM connected to FTxxx devices like the FT232, FT2232H, etc. If you aren't careful you can use it to render unusable random USB hardware connected to a root Hub in your PC that happen to be using one of those FTDI devices. Why would you want to do this to a part of your FPGA board that is responsible for configuration and UART communication? If you want to change the contents of a FLASH device connected to your FPGA FT_PROG is not the appropriate tool.
  10. If you look at DS180 Table 5 you will see a list of all of the Artix Device-Package options with HP IO Banks... none. @JColvinprovided the correct answer; that is trying to modify your Arty/CMOD ???? board to use one of the 1.2V standards is a bad idea. Perhaps you could provide a motivation for wanting to do this and someone could point you in the right direction to achieve your goals. If you really want an FPGA platform with an entire IO bank powered with Vccio = 1.2V you are better off buying a board that was designed to do that. There are UltraScale ZYNQ boards, like the Ultra9
  11. Well, as you can see those pins are not connected to anything. Some ZYNQ based FPGA boards have a PMOD or other connector connected to unused PS_MIO pins but your board doesn't. If you need a second UART you can export the unused PS UART to the PL though the EMIO and either connect the pins to PL logic or PL GPIO. JA or JB seem to be your only options for your board.
  12. Be aware that evaluation licenses are temporary.. so not very useful. What you are really paying for with FPGA vendor Ethernet IP licenses is the MAC code which all FPGA vendors provide only in encrypted form. Fortunately, you don't have to use the vendor MAC, or even any MAC for that matter.
  13. The addresses for AXI mapped peripherals are defined in the board design interface, if using that hardware design methodology. You can find all of the hardware design information in the SDK in the files that are exported to the SDK from Vivado; system.hdf and system.mss ( assuming that system is the name of your board design ). Unfortunately, the hdf file isn't readable in a text editor, but you can read it in Eclipse when the SDK is open.
  14. Ultimately, it's you the user. Yes, documentation can be confusing or have errors; and does so more often than anyone would like. When users run into these situations all that they can do is notify the vendor and hope that corrections are made. Never connect any external hardware to your FPGA platform until you've worked out the details to verify that there will be no nasty surprises. This is especially true when buying hardware from a vendor other than the one who designed and sells your FPGA platform. This is especially true when using external hardware that your FPGA board vendor doesn't li
  15. Your picture doesn't actually show where all of those wires go... Using flying leads for configuration isn't recommended. Assuming that you have the wiring correct, have you tried slowing down the configuration clock rate to 1 MHz, just to see if there isn't some connectivity with the HS3? Jamming pins meant for 2.54mm header sockets into 2 mm header sockets can cause mechanical connectivity problems. I'd be surprised if you can configure your board with a 30 MHz JTAG clock given your setup. A JTAG cable with an inline header plus an adapter to connect the pins to the Mimas-A7 JTAG header
  16. So, are you saying that you were able to configure your Mimas A7 using the HS2 cable? The recent HSx cables come with a 14-pin 2mm female header. How exactly, are you connecting the HS3 to the 6-pin inline JTAG header on the Mimas-A7? I mistakenly wrote that the Mimas-A7 uses a 75T device. It uses a 50T device. I checked and, to use the Adept Utility on WIN10 with the Mimas-A7 I did add a line for the Artix 50T IDCODE to jtscdvclist.txt that the Adept Utility uses to identify the device. I have an HS3 cable but can't locate the inline adapter or I'd confirm that my HS3 cable works wi
  17. I agree and couldn't have said it better, excluding the reference to excellence. The problem with this approach is that it stunts your growth as a programmable logic designer. It's also a walled garden that you will find frustrating to get out of once your project dreams outgrow the free IP and layers of user interaction. An opinion to consider. I'm not a believer is quick and easy. Learn FPGA development as it should be learned; as digital design. Sooner or later you will need to anyway. First, assuming that you are coming from a software development background, you need to gra
  18. Schematics rarely lie. Though in the early days of the PC IBM was famous for publishing schematics with errors, as a way to identify infringing clone copying, much as map makers use to do.
  19. The Mimas A7 JTAG header is wired in a way that isn't compatible with the Digilent JTAG cables without inserting an adapter between the cable and the board. I changed by Mimas A7 to do Synchronous 245 FIFO mode and can't use the official download application because I modified the jtag endpoint descriptor inadvertantly. This can be fixed when I get around to it. I currently am using old HS1 revA cable for configuration without issues. The Mimas A7 uses an Artix 75T device which is not one of the devices that Digilent uses. I don't recall if I had to add a device to the Digilent Adept support d
  20. Alternatively, when using the Xilinx Standalone OS you can just access gpio and other hardware in C using pointers instead of the provided library api, just as you might for a uC application without an OS. Just be aware that even the Z7010 ARM cores are fast enough to cause bus faults for some AXI interfaces, like the Xilinx AXI-GPIO IP, so you can't necessarily poll GPIO at the highest rates. Still, if you like using AXI BRAM as an interface between your PL and ARM cores, it make for a more consistent coding style. Don't try this with a linux or RTOS OS.
  21. There are shipwrecks caused by foolishness and shipwrecks caused by misfortune and shipwrecks caused by guile and noncompetitive practices. The Gates fortune was built on the graveyard of , not only competitors ( worthy and unworthy ) but also 3rd party Windows dev. foolish enough the believe that they would be given a fair shot at financial success investing in the early Windows tools and and the personal desktop juggernaut that was the early days of Microsoft. For the mainframe tycoons.. good riddance as far as most of us are concerned. For the benefit of the whole low cost computing revolu
  22. It's really unlikely that timing constraints for your UART interface IO pins are causing problems with the results. A general rule for clock logic is that the delay for combinatorial logic and routing have to be less than the clock period. With no timing guidance, even simple designs can break this rule. Default timing reporting in recent versions of Vivado are almost useless, even with good IO timing constraints. Still, if you learn how to set up the reports properly they can help track down issues. It just isn't as easy a task as the older tools made it. If your hardware isn't matc
  23. Block memory resource in FPGAs are very high data throughout and the fastest ways to transfer data, excluding transceivers. So your soft processor is the bottleneck here. If you are comfortable doing HDL design getting rid of the MicroBlaze would be a good first step. This is especially true for iterative algorithmic computations. I don't know the details of your project of course so this is just my first impulse from reading your post. I don't use soft-processors. An alternate design scheme would be to disconnect the data processing from the MicroBlaze and use a state machine to run the
  24. I took a glance at the information available for your sensors. Both use an interface board to create a voltage output with some relationship to the transducer output. Unfortunately, not much information about either the conversion board or the transducers for either sensor is provided. There are two major things to consider here. One is sensor output impedance and ADC ( including analog driver circuitry ) input impedance. Ideally, the sensor would have very low output impedance and the ADC very high input impedance. The other consideration is whether the sensor output is constant or fluct
  25. ADC datasheets are tricky to navigate even for seasoned engineers so don't feel bad about being a bit confused. Most ADC converters, and the successive-approximation type like the AD7476A are mixed signal components; they have a digital section for sending the output code to another digital device, and an analog section that connects to the circuit being measured. The part of the datasheet that you've posted refers to the digital part of the converter and isn't likely to be related to your problems. It will help if you tell us what sensors you are connecting to the AD1 analog inputs.