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Everything posted by zygot

  1. The UART is a an asynchronous interface. Your approach is correct. An 8X oversampling Fs should be sufficient, depending on how your HDL UART is designed. You might find this project interesting: https://forum.digilentinc.com/topic/20479-inter-board-data-transfer-project/ You should be able to achieve at least 12 Mbaud with a well designed UART with logic clocked at 250 MHz. There are many ways to limit the actual performance of any logic design operating on hardware. The most important is having good transmission lines between the driver and the receiver buffers. Impedance matchin
  2. FPGA support for extending applications into the analog domain have never been competently address by the FPGA vendors or their close partners, particularly at the low end of the $$$$ budget. Terasic has been the exception. For applications that are below an Fs of 100 KHz you can find hardware to do simple experiments... unless you have very specific clocking requirements. If all you want to do is develop your HDL signal processing skill then you can find enough cheap hardware to get started. If you have specific requirements and specifications then you need a hardware platform that has been s
  3. Well, you are correct that the Opal Kelly boards don't have an SMT clock in or clock out port. Also, Opal Kelly doesn't provide schematics. Normally, for me this would be a non-starter, but I've had enough past experience with their stuff to know that I can generally get to where I want to with a bit of effort. Once you buy a board you can install their FrontPanel software that includes source for their demos. You won't find any Signal Processing demos but you will find enough to use the meager resources that the boards provide... in the case of the XEM7320 this is DDR, and a USB 3.1 superspee
  4. The documentation provided by Terasic is actually pretty good. Also, there are example designs for all of the boards that I can afford to use. The exceptions are for Intel designed boards. Intel makes it really hard to find usable projects for their own boards. You just didn't look hard enough. You might have to create a user account with Terasic to access this information, but it's all there. Just because some of the older Cyclone IV or V hardware has been around for a while doesn't make the boards a bad choice. The DDC provides 2 channels of ADC and DAC that operate at higher sampling r
  5. zygot

    USB device port

    Your board has a USB UART tied to one of the ZYNQ PS UARTs, so this is a software design. If you create a project using the standalone Xilinx OS the SDK, or Vitis, has example software projects for using a UART. If you want to add a UART into your PL design that is independent of the PS there is example code in the Digilent Project Vault. I'm not quire sure what you mean by "uses the USB device (not host) port". Perhaps you could describe what it is you intend to do.
  6. No doubt that you will get a lot of suggestions on this. Without knowing the specifics of what you are trying to migrate I doubt that your choice of PS/PL AXI bus will be of consequence from a performance viewpoint. There are a lot of ways to approach this but I'd suggest trying to make your design as simple as possible. Either core in the PS should be able to implement the whole thing unless I'm misunderstanding your requirements. A fixed point HDL design in the PL would certainly work as well, though I'm assuming that your mention of Vivado HLS means that you don't want to do Verilog o
  7. The normal way that PS hardware like UARTs, Ethernet MACs, etc. get connected to PL connected pins is when you create a block design and plop a ZYNQ-7 into the design. For ZYNQ based boards this is the first step. If you double click on that block in your design it will allow you to set up the PS, including emio pin muxing. I really encourage you to do a bit of homework reading relevant ZYNQ references provided by Xilinx. You should consider searching for a few tutorials about how the ZYNQ works and creating a project. There are tutorials about how to do exactly what your question suggest
  8. It's been a while since I've played with the Eclypse-Z7 or the demos. As I recall the demo for the ADC1410 wasn't very good at showing how to tune the ZMOD to display input signals properly. I don't really have anything more to say about them that I haven't already posted. Both ZMODs have very good datasheets and design notes. The ADC1410 has a lot of modes and settings that you need to understand. Do read the available reference manuals for your ZMOD and work through the ADC signals from the output code ( which is select-able ) though the various termination, coupling, offset and gain comp
  9. The ATLYS has a GMII Ethernet PHY capable of 1 GbE data rates. This is the easiest of the PHY interfaces; even so it's not for beginners. If you've never attempted an Ethernet PHY design one possibility is to do a MicroBlaze design with Ethernet and see what HDL code the Xilinx IP produces. The MAC will be encrypted but you can slog through the PHY interface. There are other Ethernet PHY interface designs for ISE out there on the internet to be found that will provide clues as to what your design will need. For incoming data you will use the Rx clock out of the PHY. For outgoing data
  10. I've installed the 2020.2 version of Vitis and Vivado onto Ubuntu 20.04 recently with no issues ( so far ). In fact I've installed Xilinx tools on a lot of 'unsupported' OSes ( and OS versions ). VMs are another ball of confusion. I'm sure that there are uses for running software in a VM on another OS but in my experience these are pretty limited for running applications like Vivado or Vitis. I get it that trying to follow a tutorial that's written for an OS that you don't have is a problem for beginners but then again I haven't seen many tutorials that worked out exactly as written anywa
  11. It would help if you specified the FPGA board that you are using.
  12. Well, while you are waiting for someone other than me to come up with an answer I guess you have some spelunking to do tracking down how VM under Ubuntu handles the tricky business of allowing a secondary OS access devices like USB endpoints. If you are going to to use Win10 within Ubuntu you might as sell have a sense of what's going on. I'm curious as to why you, or anyone for that matter, would want to run Win10 as a VM to do FPGA development as the tools from both Intel and Xilinx work perfectly fine in Ubuntu.
  13. Sorry, I missed this part of your original post. This complicated things. I'd start by tracking down what Ubuntu sees as devices. Try lsusb -v and then dmesg | grep tty in a terminal window and see what's being reported as USB TTY device targets. I haven't tried running Win10 in a Ubuntu VM so hopefully someone else has more advice to offer.
  14. One possibility, if you are using WIn10, is letting the OS decide what the best driver for attached hardware is. You can prevent Win10 from automatically updating hardware drivers. Windows confusing FTDI equipped devices as Intel USB-Blaster devices is a big issue for me even though it shouldn't be. I don't have a USB104 A7 so I can't replicate your specific problem. Have you installed the latest Digilent JTAG support onto your Vitis installation?
  15. The LPC FMC equipped Nexys Video and the HPC FMC equipped Genesys2 are capable of doing LVDS with a selection of Vccio bank voltages. You can, and should, review the schematics for both boards. Since you don't need IP it's really about choosing the platform that has the most bang for the buck. Both have fairly large ( for budget minded customers ) FPGA devices but the Kintex on the Genesys2 really shines. High quality FMC mezzanine PCBs aren't trivial to layout or cheap to produce and since you have the platform trace lengths to the FMC connector fixed might complicate using a custom boa
  16. Have you looked at the XEM-7320? I've used it with both ZMODs.
  17. Thanks for the update. Sorry that I didn't seem to have any useful advice. I still use Vivado 2016.4 on my WIn7 box. There are a number of things that seem to work better in that version than some recent versions of the tools.
  18. zygot

    Cmod A7-15T PCIe

    To anyone wanting to do a PCIe endpoint on an FPGA board. Be aware that there are a number of boards out there with PCIe 'finger' style edge connectors. That doesn't mean that the board is something that you want to insert into your PC. Very few of these generic FPGA development boards have the PCIe slot PCB capture extrusion; meaning that the mechanical stability is a factor to consider. One possibility, at some expense is to use a PCIe adapter extender cable. I've done this successfully for multi-lane Gen 2 boards, but this too has its downsides. Another thing to consider is that the PC
  19. I see that you're back after thinking that the your design was working. Well this is a good lesson because 'working' is a slippery thing to define. The basis of Ethernet is the PHY interface. Create two ILAs in your design to capture Tx and Rx data. They are different clock domains and need separate ILA instantiations. This will tell you if you at least are getting reasonable Rx data. A complication is that for the Genesys2 the PHY uses RMII so the data is DDR. In my designs I usually have a GMII bridge so that I can see 8-bit data easily. I do a lot of work using the Ethernet PHY in
  20. zygot

    Cmod A7-15T PCIe

    There's a world separating "blinky LED" to implementing PCIe. I'm not talking about just the technical aspects of implementing PCIe in an FPGA. You will need to become proficient with an HDL like Verilog or VHDL. If you are starting from scratch I'd suggest Verilog. You will also need to become proficient at verification using a logic simulator, writing testbenches and perhaps using other formal tools. You will need to develop an understanding about how the programmable device vendors tools work and what kind of support they provide. You goal is PCIe. That's great. The 2 biggest players i
  21. Digilent has made using this board as hard as is humanly possible. Even tracking down documentation isn't easy. Keep looking. Low level drivers for both XMODs are in the GitHub repository. You can also just download the Digilent Vivado-library-master and find the low level driver code under /ip/Zmods. Since the Eclypse-Z7 is a ZYNQ board you need more than the provided VHDL source code to use the pods. I've had success using the ADC ZMOD low-level controller code with the Opal Kelly XME7320.
  22. zygot

    Cmod A7-15T PCIe

    Yes, do ask before you buy. The short answer is No. PCIe uses transceivers. You aren't going to run transceivers off of a USB VBUS power supply. I seriously doubt that the lightweight PCB used by the CMODs can dissipate the heat produced by the MGT block, which, btw isn't powered on. You don't have a way to supply a clock to the transceivers. Need I go on? ( yes, by the way I'm just getting started ) So, let's say that you implement it by creating a bitstream. How are you going to test it? Even if you had a PCIe connector available how would you intend to use it on a host? ( you
  23. The Nexys Video and Genesys2 have decent USB 2.0 connectivity. I'm not sure what you mean by 'capture system'. I've used the Nexys Video HDMI input with an HD-SDI camera and SDI to HDMI converter to capture video. Both boards have HDMI input and output ports. Before making a purchase it might be a good idea to try and build the demos for boards that you find suitable and in your price range to verify that any required IP is available for your tools version. Free IP doesn't always survive tool version releases. You can always use older tools. The only way to know if there are any unpleasa
  24. No one is going to appreciate my opinion here, but it's the best advice that I can think of. Digilent sets itself apart in the FPGA development board space by providing a nice variety of external components like FLASH, Ethernet, video, etc. There are a few things that I'd consider necessary that never appear on their boards, like SMA clock-in clock-out connectors, external programmable clock modules, etc. Pristine clocking is the first and most fundamental aspect of a hardware design and in cases like yours a requirement. If you don't have to have an ARM processing complex I'd sugge
  25. I didn't notice that tutorial. A lot has changed between Vivado 2015 and Vivado 2019.2. But you point is well taken. It might not be totally unexpected to run into snags trying to upgrade a project from one version of Vivado to another but expecting a tutorial where you build a hardware project from scratch to work, regardless of the tools version, seems to be pretty reasonable. It's possible that the original tutorial had things missing. You could try installing the same version of the tools as the tutorial used and see if that makes any difference. You might find that Vivado 2015 is a b