zygot

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zygot last won the day on May 14

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About zygot

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  1. zygot

    Video RAM in DDR

    Another thought on Linux as a platform. I have written a loadable kernel driver. It works fine on my kernel 2.6 Centos 6.2 box but is totally useless in Linux distributions with a 'modern' kernal. The sad reality is that i technology everything's a moving target. Usually that's good, sometimes that's really bad. I cook with pots that were my mother's in the middle of the last century. Even if I could find anything nearly as well made and good for cooking I couldn't afford to buy them. That's a rather silly example of bad technological advances.
  2. zygot

    Video RAM in DDR

    Yeah, that's true. All of Xilinx's IP is, at its source just RTL. So is your Intel processor in your PC that runs Vivado. DMA can sound more impressive than it is. Recently, I posted a Project Vault ZYNQ design that has no AXI HDL code and a minimalist board design. It has a couple of 2Kx32-bit 'maibox' BRAMs that both the PS and my HDL can do read/write transactions. The HDL has a 'DMA Engine' that pushes data between the mailbox BRAM and the HD application BRAM. Don't be impressed by the fancy name; it's just an address counter in one process... Be like @[email protected] when he works on his own projects... don't use AXI in your HDL designs.
  3. zygot

    Video RAM in DDR

    @Dannny, Hey, for what it's worth you've taught me something about the Mig that I haven't found out for myself yet. I guess that's the utility of having a forum where people can ask questions and get nswers from a variety of perspectives is all about. Everyone can learn things and get a little seed of inquiry implanted into the back of their minds. You never know what can happen.
  4. zygot

    Video RAM in DDR

    @Ciprian, I understand why there's a desire to stuff Linux into some FPGA designs. In fact you've fleshed out a few of the difficult problems that someone taking the HDL flow must solve on their own quite well for me. @Dannny has discovered one of the other conundrums which is trying to fit an idea into an FPGA platform as opposed to choosing an FPGA platform appropriate to your idea. Sometimes the choice of external memory designed into a board limits comes with unforeseen restrictions. You've also nicely exposed another problem in that even if you can get a non-ZYNQ platform running some form of Linux that doesn't necessarily resolve your problems. Furthermore, using the limited IP available with the MiccroBlaze comes with a problem that only appears after many weeks of work. What if you need your DDR video buffer to work differently or better? Then what? Likely, you have to do all of the stuff that you correctly point out is very hard to do. I don't know what the purpose of the design exercise is. If I had to execute a design that leveraged open source Linux source material I'd certainly want to do it on a ZYNQ platform. But the typical Z7000 family FPGA board is not a wonderful Linux platform if you need performance. Creating a custom Linux build reasonably scaled to the resources of you FPGA platform is not easy. If you are trying to work out how a processor driven DDR video frame buffer might be implemented you will end up knowing a lot more doing it yourself then relying on IP that you don't understand or can't easily modify. There's nothing wrong with slapping together a quick MicroBlaze design using available IP from your FPGA vendor, if learning how to do that flow is the goal or if all you want to do is get to a point where you've accomplished something. Having something that you can adapt to any FPGA platform or project is a different matter. Developing something that you can easily rework or improve is another matter, except that you don't realize it until you've invested a lot of time into getting to the point of having a design that you hope can be a springboard into something better. Hopefully, having some idea of the obstacles that lie ahead will help make for good early design decisions. I know, it's complicated.
  5. Mull over your sine LUT. BTW, why did you replicate 2 cycles instead of just using 1 in your LUT?
  6. zygot

    Video RAM in DDR

    @Dannny, Sorry about that. I don't have a Nexys A7 to play with so I didn't. The Spartan 6 family that the Artix replaces has a really nice multi-channel hard external memory controller as part of the deal. Sometimes progress is a step backwards... Well, perhaps it's not time to jump ship. You can still use one channel to write/read the DDR. If you later decide that you want to add a soft processor this might be able to be addressed on a system level. There's almost always more than one way to get to a destination. You may have to do more thinking about how to get there using one channel.
  7. zygot

    Video RAM in DDR

    Great! So Let's start off with a 'system' level design. You can certainly implement the simple concept as outlined in your diagram using only HDL. Let's hold off on the final goal for now. It's not only OK, but a really good idea to run through a number of smaller design projects that can then be used to implement a grand idea. So lets map out a system for testing your plan for loading some sort of image into DDR and displaying it on the VGA port. Take your diagram and add the parts that include everything that you think that you will need to do that. You also might decide that the first step would be to just implement a Mig with 2 controller channels and verify that you can do that, ignoring VGA. This would be easier and quicker. Once you have plan for how your step 1 test project is to be performed you can create toplevel HDL entity. Then you want to use the IP manager to create a native Mig external memory controller for your board. You will have to design your own read/write controllers to use the Mig. I'm mentioning this because there are quite a few details that, as an HDL designer, you will have to flesh out. If you look around you might be able to find some example code to help with implementing all of those 'black boxes'. That's the burden of doing HDL designs. The alternative is to let Vivado take care of most of the details in a board design flow, but then Vivado has control over what you can and can't do. Board design or HDL is an important first decision to make. Yes, you an add HDL to a MicroBlaze board design but while you can get so far along quickly, progress can get quite slow as you add the final touches.
  8. I glanced at your code. The lines like this one bother me: new_val := dac1_accum + sample - 2048; I wonder how Vivado implemented this. Usually, in my experience a better way to do this is to pipeline so that each '+' operation is performed on a separate pipeline version of the signal. From a coding viewpoint it appears to be straightforward. From an implementation viewpoint it looks like you have in implied latch, at least. Regardless, you are trying to perform 2 add or one add and 1 subtract in a clock cycle. Even for a quick prototype exercise this isn't a good idea. Sometimes our HDL code gets written by the parts of our brain wired for C. It's dangerous.
  9. Measurement technique is certainly critical to successful analysis of how your hardware is performing. So is the selection of test equipment. I see that your most recent plots show a high DC component. As Sigma-Delta Modulators aren't DC accurate is appears that your are trying to do measurements using direct coupling. An AC coupled load would seem to me to be more appropriate. This raises the topic of source and load impedance.
  10. zygot

    Video RAM in DDR

    Since you are using the Nexys A7 I think that the first question should be what kind of design source flow are you using. The Mig IP allows for creating multi-controller external memory designs so that's not a limitation if you are doing an HDL design. If you are using the MicroBlaze / board design then you have to work within what that provides. This approach will certainly consume more of your device resources. As I don't use MicroBlaze or the board design flow for non-ZYNQ projects I can't help with that.
  11. zygot

    PMOD I2S2 IP

    You are probably correct about that. But if you walk over to the desk of one of your compatriots who's been around for a while ( not raising the subject of age ) they will remember the old days when FPGA boards, even those from Digilent, came with one or more RS-232 ports. This was way before ARM was born but Digilent did provide code for a UART that worked well enough to include in its support. You may have to sit through a few boring discourses but the code is there, somewhere.
  12. zygot

    PMOD I2S2 IP

    I mentioned ZYNQ because it's not clear what FPGA board the person asking for support is using. You don't need to touch AXI for your ZYNQ designs. I've posted a few alternatives. The Fun with Phasors demo is but one approach. I use a UART in my designs a lot and have found that I do need a wide range of serial settings. While I don't do much in the way of RS-232 is is still a viable alternative to RS-422 for some applications and it's nice to have a UART that can function in such an environment.
  13. zygot

    PMOD I2S2 IP

    @[email protected] I looked at your IP core link. I looks pretty nifty but I have a question. Why in the world would anyone want to put an AXI bus between their logic and an HDL UART? In particular, why would they do that for a soft processor? It seems like hitching a trailer with a couple of mules to the back of your ATV in case you get stuck crossing a creek. Just excess baggage. Anyway, I'm not sure that an AXI-UART is going to simplify life for anyone needing an HDL UART core. For ZYNQ designs the PS has 2 UARTs. Almost all ZYNQ FPGA platforms connect one of them and the other can be connected to PL pins without an HDL UART instantiation. It is a nice demo of your AXI work however. I do think that the link might steer people to a useful discussion on the subject of the AXI bus. I'm a bit less sure of posts to this forum that could be viewed as trolling. Perhaps Digilent needs a special AD warning symbol. RS-232 needs to be designed to work with equipment that might have a significant baud rate error. What's the baud error that your UART tolerates? +/- 15%?
  14. Xilinx script generated code and resources provide a lot of interesting solutions to problems. Some of what Vivado deposits into your project directory is encrypted sources, but most are not particularly easy to read text, and often well worth the gander. One problem with script generated code are irritating things like std_logic_vector(0 downto 0). Still, I say you're on the right track. Just make sure that you understand what your found solutions are doing and what they are intended for. But that's just SOP.
  15. It's been a few month ago, so I can't point to sources, but there were security issues found in the popular ZIP utilities that most of us use. The .rar format didn't suffer from that particular issue. I'm just pointing out that: Choices of selecting a particular utility or format may have a reason that isn't obvious Everyone should stay up to date with security related news. It'll take you mind off of the constant SARS-COV2 news, though you should stay informed about that as well for you own personal safety, but not necessarily help in the search for a good night's sleep. Glenn's post is a very good one. Do ask why. Being curious is not just for toddlers.