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zygot last won the day on December 1

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About zygot

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  1. @Matthew Cabral I guess that you didn't read my post about EVM/FPGA development board experiences. It just so happens that I did manage to cobble together a connection between the ADS4449 EVM and a KC705, so in theory you should be able to make it work with the Genesys2. I had to use a separate intermediary adapter between the EVM and the FMC connector. The EVM had support studs that I had to remove. The whole thing didn't end up being very mechanically sound. I had to supply additional supply voltages to the EVM. To repeat warnings that I've posted before , you have to understand all of the documentation carefully before making a purchase. The ADS4449 EVM is set up for narrowband (125 MHz) operation for signals centered around 185 MHz. In theory you can change components to change this. The data interface is simple enough but you need to implement a serial interface to set up the ADC. I just used the on board USB interface so that I could use the Ti software to set up the chip. You'll want to put the ADC into test data modes to verify the FPGA interface design. This board is a good example of surprises waiting the unsuspecting or knowledgeable user. I managed to do what I needed but can't recommend it to anyone. It was a lot of tedious work. Most high speed ADC evaluation board require a special baseboard which usually has an FGPA and accompanying software support. These things are usually geared to allow testing the performance of the device, not for use in a particular application. There just isn't many options for 4-channel high speed ADC equipped FPGA boards in a reasonable price range. One possibility for you might be: Cyclone V GT Development board ( 2 HSMC connectors ) 2 Terasic DDC boards ( each with 2 14-bit 150 MHz ADC and 2 14-bit 250 MHz DAC devices ) There are more ADC options in the Intel (Altera) world and Terasic makes a number of boards with multiple HSMC connectors. I have used the Cyclone V GT board with a DDC so I can confirm that they work together. You don't need such sample rates and in theory you could use one ADC to sample 4 channels sequentially.. if you understand the ramifications. On last warning. Asking what people think about possible compatibility of products is a good way to get into trouble. It's pretty easy to be well intentioned and provide bad advise or advise that's easy to misinterpret. Unless someone has actually had success with particular boards they can't offer useful guidance. [edit] Since I mentioned the Cyclone V GT development board I should add a warning to anyone deciding to purchase one. Some idiot placed SMT devices very close to the HSMC mounting post holes. The first time I connected a board to one of these connectors I sheared off on the these SMT ICs (part of the board JTAG chain) and had to wire around it in order to configure the board.... not a way you want to discover board features. For the record it's a very good and useful Cyclone V board...
  2. zygot

    Adept software Manual ... looking for author

    @Pavel_47 , I have no experience doing what you intend to do but I suggest trying the Xilinx community forums. Intel also has a similar venue. I figure that having access to the largest set of eyes is the best chance of connecting with someone who has helpful information.
  3. zygot

    Adept SDK C# Library

    In case anyone is unaware of this. DEPP is relevant to the older Digilent boards ( ATLYS, GENESYS) using the Cypress FX2 USB endpoint solution for asynchronous communication. All of their newer boards use (sigh!!!) FTDI USB endpoint devices. I suspect that the posted DLL is of little use to very many people.
  4. zygot

    Adept SDK C# Library

    Except for those posting here.... but one thing common to all who off advice, at any price, is that their efforts are likely to result in resentment rather than gratitude.... Unless it's on a scam topic... CMM Anyone?
  5. zygot

    Adept software Manual ... looking for author

    Hi @Pavel_47, I'm afraid that I still don't understand what your goals are. If you are interested in configuring FPGA devices Xilinx device documentation is excellent and there are application notes and a few demonstration projects. If you want to pass data between a configured device and a PC xc6lx45 recently posted a project showing how to do that using the BSCAN primitive. I can't think of other uses for JTAG. Designing a boundary scan system to do say, a complete PCB test, will require a bit more research. There is an open source JTAG effort that might be instructive. IEEE 1149 covers boundary scan.
  6. zygot

    Adept software Manual ... looking for author

    @Pavel_47, I've noticed a few of your recent posts and understand your frustration. Might I suggest that the Adept software isn't the only possible approach to using the USB resources. I've used the FTDI driver APIs with the Nexys Video and there's a very recent project posted to the Project Vault that's an excellent tutorial for doing what you appear to be interested in for the CMOD. Before venturing into specifics related to any USB device or API you have to have to have a good understanding of USB concepts and protocol. There are other resources for that.
  7. zygot

    VHDL: Why are those 2 variants not equivalent?

    Be careful with nested if..then..else statements. This structure implies priority. In ISE you can view the synthesis results in an RTL view to see a schematic of how it interpreted your code. Did you try an simulate the two variants? You haven't found a bug in either ISE or VHDL but figuring this out might be a valuable exercise. In VHDL the ':=' and '<=' assignments are not equivalent
  8. zygot

    busbridge3: High-speed FTDI/FPGA interface

    @xc6lx45, Well, thanks for the support. Again, it's a fantastic tutorial and highly usable. As I mentioned I intend to massage it a bit and perhaps add my own twist to the interface for a future project.
  9. I had intended to include these scope pictures: One shows the DAC waveforms after the first DAC packet updated the waveform buffers. The waveform buffers are initialized in the configuration bitsteam. The other shows the latency from when the ATLAS gets an ADC packet to when a DAC packet is sent.
  10. zygot

    busbridge3: High-speed FTDI/FPGA interface

    Yeah, my eyesight isn't that great to spot the parens on my own... the source for my last build (what was the latest source from GIT) was not the updated version. The fixed lines stopped throwing exceptions after I put the rest of the code back to yours to run everything. I did download your latest this morning and installed it into a fresh directory. Built the bitstream and C# application. I don't get any error but am not sure what I am looking at. Your USER2_demo runs twice but doesn't provide any notification of success... so I guess that it passes. The application repeatedly prints out the lines: configured test register delay... round trip time... margin 1: margin 2: the reported round trip times seem to be around 0.260 ms if the CMOD is plugged into a hub and around 0.06ms if I plug the CMOD directly into a PC USB port. The one LED does blink at a 1 sec interval. I never do get to the "All tests pass..." declaration that I'm expecting from the program.cs source. For what it's worth, last night as I was playing around with the SharpDevelop debugger it appeared that the second call to getUInt32 at line 505 in bb3_lvl4_memif.cs was where the exceptions were happening. I'm going to try an see if I can make the CMOD Verilog do something a bit more interesting than blink the LED... Sorry for the troubles...
  11. zygot

    busbridge3: High-speed FTDI/FPGA interface

    The committed lines seem to be there. If I uncomment the memTest32 calls and comment out the try/catch I get the following: System.OverflowException: Arithmetic operation resulted in an overflow. at busbridge3.memIf_cl.getUInt32(Int32 offset) in c:\Projects\busbridge3-master\busBridge3\bb3_lvl4_memIf.cs:line 362 at busbridge3.memIf_cl.getUInt32(Int32 offset, Int32 num) in c:\Projects\busbridge3-master\busBridge3\bb3_lvl4_memIf.cs:line 373 at busbridge3.memIf_cl.memTest32(Int32 memSize, UInt32 baseAddr, Int32 nIter) in c:\Projects\busbridge3-master\busBridge3\bb3_lvl4_memIf.cs:line 505 at Program.Main2(String[] args) in c:\Projects\busbridge3-master\busmasterSw\Program.cs:line 162 at Program.Main(String[] args) in c:\Projects\busbridge3-master\busmasterSw\Program.cs:line 8 I'm running WIn7 64-bit as well.
  12. zygot

    busbridge3: High-speed FTDI/FPGA interface

    There's a problem with your memTest32 function... haven't found out where the overflow is but possibly a cast issue ?
  13. zygot

    busbridge3: High-speed FTDI/FPGA interface

    I created an executable using your sharpDevelop_build directory but got the exact same results as the project that I created. Commenting out the try/catch lines just created an exception in the memif without the graceful termination. I'll try and debug but it may take awhile. I'm running in WIN7 (far far away from the internet )
  14. zygot

    busbridge3: High-speed FTDI/FPGA interface

    @xc6lx45 Hi, I had no issues creating a bitstream in Vivado 2018.2 using your (imported) project file. While trying to recreate your project I ran into a snag with the C# code. I have VS2010 tools so of course your project files and solutions are unusable. I did manage to use the sharpDevelop tool you suggested. The executable configured the board and then threw an unhandled exception... (Arithmetic operation resulted in an overflow) but still terminated gracefully. I'm afraid that my C# skills have become rusty. I had to modify the path for the top.bit since I was running out of a different directory than you did ( I had to create a new solution project); simple enough to resolve. Let me make a few suggestions for such projects: Identify exactly what tools (versions) you use to create components Since Microsoft tools are notorious for not playing nice with other versions of itself you might want to anticipate that most users will have to do a work-around; not a complaint, just a thought. Assume that you audience might have a different development trajectory, especially for PC software, than you did when developing the project. I got too close to quit but so far haven't accomplished a verification that your project can be recreated. I know that you are interested an any feedback, as I am for any projects that I've posted. regards
  15. zygot

    High speed output on PMOD ports

    I hate myself for having to defend any use of those silly differential PMODs but I'll make the following observations: The FMC is a very complicated high density connector designed to connect to a well designed mezzanine card thst's plugged into it. It's NOT a general purpose GPIO connector suitable for breadboarding a signal source to external devices. You likely don't want or need the complexity of doing a ZYNQ based design just to put out a couple of PWMs. I use and like the Zedboard but it's not what you want. There are much cheaper solutions available from Digilent with those (usually $%^!) differential PMODs. It's unfortunate that Digilent can't be bothered to create pdf versions of it's User's Manuals any more so you have to do online comparison of boards. I looked at the Arty A7 board and they don't mention the usual toggling rate verbiage you will find for the description of the high speed PMODs that user's manuals for other boards have... but I doub't that the performance is all that different for your needs. You've done something that I've been unable to do, which is find a use for one of these things. Oh, and no your board doesn't have a high speed PMOD.