zygot

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About zygot

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  1. I get the feeling that you are confusing the MicroBlaze soft-processor with the FPGA. If you want to use MicroBlaze then the SDK (Vivado 2019.1 or earlier) has example C/C++ code for using the UART in a software application. Your MicorBlaze software can do what ever you want it to do. If you don't want to use a MicroBlaze you can still have a PC control FPGA logic via a UART but you'll need to know how to write VHDL or Verilog. You don't need an RTOS to do this. Commandline statements like ./Helloworld are specific to Linux. Running Linux on a MicroBlaze is a whole different level of work
  2. MicroBlaze or NIOS might be required if you are constrained to doing design using the Xilinx or Intel soft-processor centric IP. I haven't had the need for a soft-processor for a few decades; and I'd have used an ARM based FPGA it it were available. If you look through the Digilent Project Vault you'll see source code for connecting your FPGA design to a PC through a UART in quite a few of the posted projects. The UART is the most trivial way to connect your FPGA design to a PC, except for the PC application if you are using Windows and C or C++. Python not only is easier but works on Lin
  3. Perhaps you just chose your words badly but it's important to assign the correct IOSTANDARD to every pin used in a design. Use the schematic to see which IO bank each pin that you are using is connected to. The schematic will show what the bank Vccio voltage is associated with each pin and therefore constrain your selection of IOSTANDARD assignment for that pin. Furthermore, if you want the design to work properly the IOSTANDARD assignment must be compatible with the logic family that the pin is connected to. Ensuring compatibility is not only important for ensuring that a design will work but
  4. I forgot to mention this but always compare pin LOCATION and IOSTANDARD constraint assignments to the schematic as a verification step. Yes, this is a problem when pin connections aren't shown on the published schematic. Unfortunately, since moving to the FTDI devices Digilent has decided to hide this information. The schematics are generally correct though it's possible that a replacement part isn't reflected in the latest published schematic. Some vendors are good at publishing complete information on all PCB versions and some aren't. In general the schematic comes from the PCB files so it r
  5. No, don't do that. You can have multiple external clock sources, and your designs can use, or ignore, any of them. The 12 MHz clock is necessary for USB connectivity for configuration and a UART channel. I do think that assigning two of the GPIO pins as RxD and TxD as connections to a separate USB TTL UART is a very good idea. It will give you a communications channel that doesn't get used by Vivado Hardware Manager. You can't use it with an ILA but you can use it with you own debug code, and very often this is a better way to debug FPGA designs. What I meant by commenting out location as
  6. Yes, so your new constraints file must identify the new external clock input with a pin location associated with whatever your 25 MHz clock is named in your design. You should also add a timing constraint. You can use the default constraints as a guide. If your design has a clock input named clk25m it would look something like this: set_property -dict { PACKAGE_PIN XXX IOSTANDARD LVCMOS33 } [get_ports { clk25m }]; create_clock -add -name new_clk_pin -period 40.00 -waveform {0 20.00} [get_ports {clk25m}]; Just be sure to comment out the original pin location constraint you are ass
  7. Well, you could do a search on the Digilent site for Eclypse-Z7 for comments and exchanges. I've posted projects using ZMODs with some useful information in the Project Vault section: https://forum.digilentinc.com/topic/20299-fun-with-phasors/ https://forum.digilentinc.com/topic/20331-more-fun-with-phasors/ I've posted about other projects here: https://forum.digilentinc.com/topic/20153-capture-4-channels-of-120-million-adc-samples/ You could also view my profile for relevant posts. It's hard to track down all of the interesting posts related to the Eclypse-Z7.
  8. Welcome to the world of FPGA development. The AD776x class of converters are pretty nifty for the right applications. I've done what you want to do for the AD7761 EVM, which is the AD7768 16-bit little brother, for the Nexys Video and Genesys2 boards. At the maximum 256 KS/s conversion rate across 8 channels for the 24-bit converter AD7768 this works out to about a 6 MB/s sustained streaming data rate. Getting this to a PC will be a bit more challenging on the Zedboard as you'll need the Ethernet interface. ADI has some pretty good FPGA support for its evaluation boards but I wrote my own HDL
  9. zygot

    USB 2.0 HS

    Some interesting information: The datasheet for the Digilent Digital Discovery lists the FPGA device as a XC6LX25-2C5G324, a -2 speed device. According to the Switching Specifications for this device: Fmax for BUFH is 375 MHz Fmax for BUFIO2 is 500 MHz The maximum PLL output frequency is 950 MHz The maximum LVDS ISERDES2 (retimed mode) data rate is 750 MHz.
  10. As a generalization I agree. The double clocked synchronizer is common practice but not necessarily robust enough for all applications. Really this topic can get quite complicated. As for dual clock FIFO flags there are known timing uncertainties and usually you can avoid them in a system approach. I'm in total agreement with @[email protected], if I'm reading him correctly, is suggesting that adding complexity to a complicated design approach is asking for more issues ( more difficult issues as well ) to figure out and resolve than anyone really wants to face. Elegant alternatives to complicated so
  11. zygot

    USB 2.0 HS

    @RomanB, I haven't used this instrument but I read through the literature. I'm doubtful that you can use for capturing traffic on the DP and DM lines for a number of reasons. The most important ones are that the Digital Discovery isn't meant for differential signalling. A bigger hurdle is that USB 2.0 uses the UTMI signalling standard that is quite complex; there is no Xilinx IOSTANDARD that I know of that is compatible with UTMI. A bigger problem is that asynchronous sampling of a 480 MHz signal with Fs = 800 MHz doesn't quite do the job. Could someone make an adapter for doing this? I'm
  12. zygot

    USB 2.0 HS

    I see that you still don't have an answer. That may be because no one knows what product you are talking about. I get no hits for "Digilent 240-127" on the site search.
  13. zygot

    USB 2.0 HS

    If you want to capture USB bus traffic you need to buy an instrument designed to do that. I've not seen anything to suggest that Digilent sells these.
  14. My personal preference is to only use ZYNQ where is it essential... and that is infrequently. But just be aware that the Genesys2 is not ZYNQ based like your starting point. One additional note: The Kintex 325-T is not supported for free by the tools so you need a license. Fortunately, Digilent supplies a voucher for a limited device license. The license lasts forever on the node-locked development platform where it's installed and allows for 1 year's worth of Vivado tool version changes so plan ahead. The good news is that the part has been around for a while and I've used ISE and the earlies
  15. The solution to your problem is identical to one encountered in software development. In instead of using 'magic numbers' in your code use abstraction. In regular software you can reference a calculated constant or variable. In Verilog or VHDL you can use generics or parameters. A simple way in VHDL is to define your count as different constants each calculated for a specific clock rate. A better way is to use the IEEE.Math library and calculate the value as a constant and reference that in your code. If you use a generic for the clock rate this is handled for you during synthesis. I'm mention