zygot

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zygot last won the day on March 13

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About zygot

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  1. Why is my Process getting triggered with no change to the sensitivity

    @hamster, No worries about irritating me... it's more a situation of being self-irritated... when something just doesn't seem right is sticks around in my subconscious. So after reducing the source to the basic functionality, without the ILA, we probably agree that understanding what's going on is an interesting problem to analyze. I did see that I forgot to comment out a few lines in my constraints file. I was thinking of posting the source as an "interactive discussion" on the tutorial section of the forum so as not to co-opt this thread. I think that the resulting discussion might be interesting. Any encouragement to do so? I realize that simply telling someone asking for help how to write code that might move his progress along might be useful in a limited context but even more useful might be testing out what the experienced folks "know". On one level is the VHDL language and extensions, and on another is the FPGA architecture and tools. In my experience the sum of those is more complex than the parts. Yes, I think that you are (generally) correct. The synthesis tool doesn't complain about the source code at all except that the counter isn't in the sensitivity list. As to VHDL and writing synthesizable code that does what you want it to do the source is problematic. Of course the synthesis tool isn't magic and has limits in it's ability to interpret the intentions of source code. But it would seem that the synthesis tool has decided that you want something that looks a lot like a ring counter.. perhaps. A problem with trying to use a counter that is essentially a feedback loop is controllability. Even if you were to assign the logic to specific LUTs it would be difficult ( not impossible ) to control the count frequency and get the place and route tools to understand timing. It would be more difficult to use this structure effectively. The reason that I decided to post the previous alternate source is to spur conversation for the sake of education. Even those of us who think that we know things should step back from time to time to test what it is that we thought we knew in the context of our current experience. Your original question is actually a lot more complicated and interesting than you might have expected. As to the next step in "improving" the original source it would seem that using a clocked process, event or rising_edge approach would be better. But what's the difference? Does any approach work or have the same outcome? Hmm...
  2. Why is my Process getting triggered with no change to the sensitivity

    @hamster's statement shown above has been bugging me ever since I first read it.. about once a week it comes into my consciousness and irritates me. I contend that hamster's comment is just plain wrong and that the only reason that the poster got any thing to configure his board with was because of the ILA requiring a clock. I still think that what the original ILA output was showing is a ring counter sampled by a 100 MHz clock.... I realize that the poster didn't like my comments but I decided to re-create his original code project in order to restart the thread commentary in a more helpful direction. So here's what I did. I made minor modifications to remove the ILA from the code as it is causing confusion as to what's going on. Instead I send out 24 of the 32 counter bits to IO so that up_test isn't optimized out of existence. I then tried to create a configuration file using Vivado 2016.3. Here is the BITGEN error message: ERROR: [DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop Alert - 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any net in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [net_nets <myHier/myNet>'. The cells in the loop are: JA_OBUF[0]_inst_i_7. Below are attached the project sources as modified by me. I invite anyone interested in recreating the project to see the results.... btn_test.vhd btn_test.xdc
  3. Cmod A7-35T Demo Project

    @stempelo, It took a while to find out if anyone has tried out any of my posted projects... but thanks for the feedback. The project is as unambitious as one can get but does demonstrate an alternate to the standard Digilent demo and a lot easier to modify... plus it's relatively immune to Vivado versions. This was one of the first projects that I did and it had specific goals. You might find the S3 Starter Board Programmer project interesting as well as it features the CMOD-A7-35T in a different role and has more HDL example code.
  4. @JColvin, I've been using ISE 14.7 on Centos 6.x for some time and it does support the XC7A100T-1CSG324C device. Honestly, I don't recall if it's the full or free version. I have not however tried targetting that device as I don't have any boards using it.
  5. My first Zybo/7010 project

    I beg to differ and have a lot of completed projects that prove otherwise. I do suggest that all tri-state capable bus driver logic be kept to the toplevel of your HDL code. For logic down the hierarchy use uni-directional buses. Again, I beg to differ. Resets are not at all as straight-forward as one might imagine. Regardless as to how complex or simple you believe that your reset logic is the designer has the burden of understanding possible failure conditions and designing to mitigate them. Even very seasoned digital engineers get the analysis wrong. Though I don't have any C64 experience this appears to be a nifty little project that might grow into something not so little. I know that it isn't the only one.
  6. @pcdeni, I feel your frustration. I'm thinking that you probably have some other requirements other than "lots of GPIO pins". I can think of cost, PC interfaces like USB, Ethernet, DDR memory etc. As I've posted in other threads I've used the CMOD-A7 and Terasic DE0-Nano (Altera) for many quick and dirty projects. Understand that if you want to drive a lot of signals out of your FPGA board you need a board with a suitable power supply and a way to handle heat dissipation. The previous two boards that I mentioned are, in my opinion, rather weak in this area for a wide range of uses. The Xilinx boards often come with an LPC and HPC FMC connector providing lot's of IO. Opal Kelly has offered FPGA boards with limited functionality but lots of GPIO if you used their breakout boards. Their price point is higher than Digilent's. I've used their boards successfully for rapid prototyping. There are some crowd funded boards. Crowd Supply has the Snickerdoodle ( Mouser sells an older version of the current board ) and the Syzygy. I have the latter board but so far there are no PODS available to connect to the main board. Digilent's older boards have a lot of IO though you will probably need to create your own PCBs to use the IO connectors. Actel ( formerly Microsemi, formerly Micrel and now Microchip ???) has some boards based on older IGLOO technology with IO. Of course I don't know how many or what kind of IO you need. There are Indian and and Asian outfits offering boards. There is also Trenz boards some of which are inexpensive and available from Digikey. I am loathe to get into the recommendation game as everyone has their own needs and requirements. I can only speak about what I know from experience. Keep looking. P.S. I would recommend that you not only look at data sheets but look at user's forums, vendor support, etc to get an idea of what to expect. It's been my experience with many embedded platforms that what you get is not always what's advertised. Buyer beware as the lawyers are fond of saying....
  7. Nexys Video with Xilinx XM105 FMC Debug board?

    @Kenneth Dyke, For the specific case of the XM105 if you aren't using the programmable clock and all of the FMC signals are outputs driving a high impedance load like analyzer pods then the default Vadj value might be OK. My point is that you need to read the Nexys Video documentation about setting Vadj, read the XM105 User's manual and schematic and make sure everything is good before connecting and then powering the two boards, especially the schematics of both boards. I always double-check everything before powering an FPGA/FMC combo and powering it on and configuring it to run an application. Understand that on the Nexys Video the FMC differential lines are laid out as differential lines and on the XM105 they are laid out as single-ended signals. If you intend to drive a lot of outputs simultaneously then I suggest that you understand the references to simultaneously switching outputs that all FPGA vendors have. If any signals are driven into the Nexys Video board through the FMC connector, such as the differential clock, you have to decide if it's a problem for the Vadj IO bank even if the pins are not being used in your design. Though you might get opinions here about that I suggest you refer to Xilinx literature for the answer. These refer to the
  8. Nexys Video with Xilinx XM105 FMC Debug board?

    Vadj works differently on the Nexys Video than on the Genesy2. Before trying to used an FMC mezzanine card ( and after reading all of the material including schematics ) you need to understand how Vadj works for your board. Again, the Differential PMOD Challenge isn't just about PMODS. It happens to target both the Nexys Video and Genesys2 boards and has some usable guidance for those prone to "smoking" in the lab because they are in too much of a hurry to see something happen ( like puff-f-f-f-f !!!) Oh, and one more thing I forgot to mention: I highly recommend that you mechanically secure FMC mezzanine cards to the carrier board using stand-offs and screws to avoid expensive Ooops! *??!!!?*(&$ moments.
  9. Nexys Video with Xilinx XM105 FMC Debug board?

    Yeah, you need to read the information provided by manufacturer of any FMC mezzanine card you plug into the FMC connector of an FPGA board. At least you need to know what Vadj needs to be set to. Never plug a new board into your FPGA FMC connector and power it onto see what's going to happen. Never hot-plug an FMC mezzanine card. @malexander is correct in that you have to connect the JTAG chain correctly in order to make the JTAG chain work. I've used the XM105 board with Genesys2, Nexys Video, KC705 boards with no issue... but then again I read the documentation first. From the README.txt in the Differential PMOD Challenge project: - IMPORTANT! Use a jumper to short TDI and TDO on HW-FMC-105-DEBUG board J5(6) to J5(7) so that the JTAG chain integrity is intact. You can destroy your FPGA board easily by attaching an FMC mezzanine card. Know what you are doing before powering on a system so configured. P.S. I recommend that if you have or want to use the XM105 Debug Board you download and read through the above mentioned project files in the Digilent Project Vault. At the very least you will find that I've shown you how to configure the programmable clock. Note that the Python script that runs the project has been updated to fix a few issues with clock programming and a later version is included in a later project. If you want an almost unusable project to program that clock Xilinx has code to do that.
  10. a7 external clock

    To all, I got this one wrong. Unfortunately, I dealt with my faux pas on a different thread.... but @xc6lx45 is correct... as obviously others have found out. Unfortunately, when there are multiple threads talking about the same topic it's hard to backtrack and fix mistakes. Apologies to all.
  11. ARTY Z7-20 board I/O output level

    @karimia, It's hard to provide an answer with so little information, though I suspect that you can figure this one out on your own. What pins on the Arty-Z7 are you using for the interface? What servo amplifier are you using? Where are you probing? Where is your ground reference point? What IOSTANDARD are you using for the FPGA output pins? What IO current have you set for those output pins? What is the problem (with the servo)?
  12. @Aniq, Yes, there are other boards with HDMI interfaces. I forgot that the Zybo had VGA out and a bi-directional HDMI port. Generally these cheaper boards don't have HDMI buffer/equalizer devices but the still may be OK for your needs. Read the board user manuals and schematics to get a good picture of the differences. Ultimately, I can't, nor do I want to make a selection for your budget and needs.
  13. Heat Created by Arty A7

    @Bryce, What's important is to limit the FPGA substrate temperature to acceptable levels. Fortunately the Series7 devices all have the ability to measure this using the XADC module. I make it a habit to include monitoring substrate temperature measurement capability in all of my non-trivial Series7 FPGA designs. Vivado can help with the analysis of temperature rise for your design but the best place to do this is in the hardware.
  14. @Aniq, The Atlys has HDMI in/out. DVI and HDMI are similar enough that there should be no problem using an adaptor/cable to span those standards. I've used DVI-VGA adaptors that (used to) come with GPU cards but not with the Atlys. I don't know of a reason why this couldn't be done but I can't claim to have done it either. I've used the Atlys for many years and like the board a lot. I will say that the Spartan6, and I'm very fond of that family, has aged a bit with respect to the Artix in terms of block ram and other resources. Still the Spartan6 on the Atlys has better IOSERDES performance than the Artix device on the Nexys Video. Both of those boards have similar HDMI interfaces, though the Nexys Video uses a different buffer/equalizer for HDMI input. You can't get an FPGA board with a more generic interface.
  15. I'm assuming that @subasheee is trying to do streaming rather than burst FFT analysis. I haven't read enough to understand how the core handles "frames" of streamed data but for sure the user needs to read and understand PG109. I always get nervous when using some else's IP that handles the details "behind the curtain" and doesn't explain the consequences... which is why I generally prefer to create my own IP. Admittedly, I haven't tried coding an FFT in logic. Well, a long long time ago I did work on an FFT implemented in ECL logic... but that was a long long time ago...