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zygot last won the day on July 31

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About zygot

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  1. zygot

    Genesys-2: Ethernet Interface - design migration not working

    @xilinx.fpga.user, Hi. I happen to have both boards and have quite a few successful projects using the Ethernet port on both. First off you need to understand that the KC705 Ethernet interface is GMII and the Genesys2 is RGMII. This makes the Genesys2 a bit more challenging. Even if you have included the requisite DDR data, control and clocking elements to your port the timing constraints will have to change. Poor timing constraints will break your interface and likely other things as well. I don't use embedded processors ( except for ARM based ZYNQ ) nor do I use the board design flow so I can only offer hints as to a solution. Also, I don't tend to support triple-speed Ethernet for my projects, just Gigabit speeds. good luck, with a bit of effort you can succeed.
  2. zygot

    Implementation in fpga and choice of pins

    @slearn, I noticed that this post is similar to another one in which the target is possibly a Virtex5 FPGA. Asking hardware interface questions on a forum like this and providing partial or incomplete information as to exactly what you intend to do is a good way to get bad advice and into trouble. In the interests of smoke-free FPGA development could you be a bit more specific as to what you want to accomplish. I think that I have an idea as to what your idea is... but knowing is better than thinking. In the diagram I notice that one of your inputs is unconnected. Without any other information to work with my only suggestion would be to read the FPGA data sheet and supporting materials to understand what the input pin dc specifications are. Driving any FPGA pin beyond those limits will damage your device.
  3. zygot

    Digilent CMOD A7 Disconnects and/or does not Program

    When working in Windows 7 I use the Digilent Adept Utility which is a very nice and robust program. This is mostly what I do when using the CMOD-A7. When working in Linux I do use Vivado but make sure to terminate the Hardware Manager as soon as it has finished configuration. I never have an issue with the CMOD-A7 USB connection detaching now that I've moved all USB UART operations to an external device and Vivado Hardware Manger is not running. I have tried without success to replicate any sort of association with this issue and a particular cable ( I've got a lot of USB cables on hand.... ). This is the only FPGA product that I have experienced this issue with. I almost always us a USB HUB ( USB 2 or USB 3 ) when working with FPGA boards.
  4. zygot

    Beginner DSP Projects

    Yes Dan he certainly would agree with your advice. Test, verify, test, verify. Let it be your mantra. Test and verify the main result that you are looking for. Test and verify all of the component parts ( particularly in logic ) in case you want to reuse any modules or components. Test and verify corner cases. Test and verify consistency of results between all of the implementations. For the logic implementation there will be more subtle and complicated aspects to consider and test for. Assume nothing. If all of this doesn't sound like fun ( I'm taking the long view by using that word) ... perhaps consider a different way to spend your free time. Oh, and I forgot to mention the most important part. Don't do it for self-defense. You can learn a lot more during the test and verification stages... you know, the part where most people have gone on to other things assuming that everything works, than you can learn during the basic design processes. Testing and verification generally requires another level of awareness to issues not obvious in the original conceptual stages. That's my experience.
  5. zygot

    Beginner DSP Projects

    I'll offer a somewhat alternate view from the one that @xc6lx45has provided. In commercial practice there is a lot of DSP work done on FPGA devices. I would agree with the sentiment that I am inferring from xc6lx45's comments above that doing DSP in FPGA is really hard. It is not for beginners as you have to understand and account for all of the minutia without high level canned code ( libraries ) that are available in say OCTAVE or C libraries. I would respectfully disagree with most of the other commentary above. DSP on and FPGA is fun once you have a certain amount of expertise. Riding a unicycle is fun for a few individuals but certainly not something that I would enjoy ( I don't enjoy bleeding and bruising...). In my experience the typical approach to DSP in an FPGA is to test an algorithm in MATLAB or OCTAVE and all of the high level keywords that are available. Then devise a simpler easy to understand algorithm in OCTAVE just using basic math and if..then..else type statements that is good enough to accomplish the task at hand. You'll have to understand the basic math and difference between floats and fixed point ( and binary fixed point for that matter ). That simpler OCTAVE coding will be your map to implementing a DSP algorithm using the resources available in an FPGA. If you start off with something too complicated you'll get discouraged, quit and feel bad about yourself. That doesn't mean that you can't do some interesting things. I suggest that you start with a simple filtering ( no feedback ). Try to describe your idea in OCTAVE and then figure out how to do it in digital logic. OCTAVE can help design the coefficients. After you have working HDL simulations compare the HDL simulation results to the OCTAVE results. You don't have to do fixed point representation in OCTAVE to see if you are close to being correct. I spent many years doing DSP assembly coding for actual DSP processors before trying to implement DSP in logic. I would strongly encourage those interested in DSP to get some expertise in something like MATLAB, then C coding for a DSP processor using canned libraries ( look at Texas Instruments for resources ), and lastly trying to to DSP in logic. Of course, if you haven't mastered FPGA logic development this could be tough slogging. I certainly helps to have some basic and advanced experience instrumenting and debugging your logic on a working FPGA platform before trying to implement complex designs. I've mentioned this in another thread but understanding DSP theory using a MATLAB or C libraries that hide all of the hard stuff is one level of "understanding". Being able to implement an equivalent DSP algorithm using basic math and flow control such as the if..then..else commands is quite another level of "understanding". If you have reached the proper level of "understanding" then you might well find quite a bit of enjoyment and fun in doing DSP in an FPGA.
  6. zygot

    Digilent CMOD A7 Disconnects and/or does not Program

    Yes this is an issue with the CMOD-A7. It is not an issue with cables ( even if Digilent would wish it to be so). It is an issue with the interface on the CMOD-A7 and a particular issue when Vivado hardware manager is opened ( for instance in trying to use the ILA feature ). Some problems, even those that shouldn't be hard, take Digilent years to resolve. I've stopped trying to use Vivado ILA or the USB UART with the CMOD-A7 . I do use something other than Vivado to configure the CMOD-A7. I do connect a separate USB UART cable to 2 spare IO pins to have nice uninterrupted productive UART sessions with my FPGA application. This issue has been known for a few years now. It took me almost 3 years to get the Genesys2 documentation free from silly errors but I kept after them until someone actually looked into the problem. I suspect that this problem cannot be resolved retroactively for current customers.... but no one is paying me to figure out the exact nature of the problem.
  7. zygot

    Zybo serial port in Ubuntu

    @jacobfeder, Here's some handy tips for using serial ports in Linux Open a terminal window in Linux Find out what USB devices have been enumerated: Enter the command 'lsusb' to see a list of enumerated devices. You can get more information by adding -v or -vv command line arguments Find out what Serial port devices are available: Enter the command 'dmesg | grep tty' to see what serial ports are available and what name to use. If you are not sure what device is what try using the dmesg command with the USB UART disconnected and again with it connected. If you run Putty and hit the open button you will either get the screen that you mention if Putty successfully connects to an available device with the specifications you assigned to the current Putty session. Otherwise you get an error message and Putty exits. Now that you have a connection all that's left is to have a conversation between the computer and whatever is connected on the other end,. If what's connected on the other end is listening, try typing into the Putty terminal window and hit enter. If the connected device is able to transmit you should get some sort of reply back. Of course if Putty is connected to the wrong serial port that's a problem. Here is an edited example session telling me to use Putty with ttyUSB0: lsusb Bus 005 Device 003: ID 067b:2303 Prolific Technology, Inc. PL2303 Serial Port dmesg | grep tty console [tty0] enabled serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A 00:0b: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A usb 5-2.1: pl2303 converter now attached to ttyUSB0 happy communicating!
  8. Hi @Nikhil Singh, As you know the .ucf format is associated with ISE, not Vivado ( the Spartan 3 family isn't supported by Vivado ). This project has some examples of the .ucf format: https://forum.digilentinc.com/applications/core/interface/file/attachment.php?id=3063 IO_EXPANDER_R3.zip Note that the location constraints in this project are not likely appropriate for your board, but you can see what the basic syntax is. Use the schematics for your board to determine pin locations. You can find the complete project source in the Digilent Project Vault project titles "Turn your Nexys Video into a Development Platform". I suggest that you use the Xilinx Documentation Navigator to find documentation on designing with ISE.
  9. This analysis is correct. What you should do depends on the display you are using. Get the datasheet for the display part that you are using and make sure that your design meets the specifications for voltage and current. Knowing is always better than guessing. You don't have to drive LEDs at maximum current to make them usable. I like xcls45's idea of not using a decoder though I like your thought about having an external device supply the drive currents. There are a number of possibilities here ( like an 8-bit bus driver ) though this might be overly cautious and will certainly make breadboarding ( if that's what you're doing ) more time consuming. If you are driving one display that is one thing. If you want to drive 8 displays you may want to think about a way to use fewer FPGA pins.
  10. Even though this might be true what's important is the thermal considerations and hence substrate temperature. A large component of overall energy consumption of an FPGA is switching those IOs. Thermal issues cause voltage regulators to fail as well if heat can't be dissipated properly ( since you raise the topic ). There's no on-board temperature sensor for Spartan 3 devices. As a general rule I use an external driver for high current applications; they are certainly cheaper and easier to replace. Having said all of this I suspect that driving a couple of seven segment displays using the minimum IO current won't be a problem for your board. This might not be necessary... but it certainly is a good idea as a prophylactic practice, especially when used in a development/hobby environment and when placed close to the pins or balls using the smallest SMT package that can handle the current. Accidents and static discharge happen. Proper termination is also good practice.
  11. @Adriann, As I recall the minimum source/sink current for the Spartan 3 is 12ma ( it might be 6 ma ). But it it up to you to get the datasheet, look in the DC characteristics and verify this. Always take this advice even if someone offers and answer. As to how much current you can safely drive on multiple outputs the answer is more complicated. It depends on a lot of things like which bank they are on, how many IOs are switching simultaneously, how well the FPGA is connected to a thermal sink, etc. Again, whether or not you want to set the IO to maximum current requires some knowledge of the specification for your part and analysis.
  12. zygot

    Programming Artix 7 without JTAG using GPIO pins

    Zygot: " "
  13. zygot

    Programming Artix 7 without JTAG using GPIO pins

    Questions like the one posted to this thread cause me a bit of anxiety as it's not quite clear that providing clues isn't abetting nefarious activity. It certainly strikes me as curious that someone wants to configure a board that isn't a known development kit and with a non-obsolete device and no obvious way to configure it. I just have that uneasy feeling...
  14. zygot

    Programming Artix 7 without JTAG using GPIO pins

    I wasn't going to think about this question but as @xc6lx45 already has and concluded that the board is set up for Master SPI I'll bite. ( I was thinking that you wanted to use any available IO pins for configuration.... fortunately for you xc6lx45 wasn't so lazy. Read the datasheet for the device. Read the Xilinx configuration reference manuals and tutorials. Look over my project in the Project to configure a Spartan 3 board using the CMOD A7-35T for a head start on a possible approach. You'll need a different board if you want to replicate my approach as the configuration file is considerably larger than the 512KB SRAM on the CMOD A7; but there are certainly ways to solve that problem. You'll need to use a different configuration method than I did. If a PROM with an SPI port can spit out configuration data then so can a logic design ( Assuming that there isn't some undocumented magic sauce... and that could be the case I suppose; I've not done SPI configuration before ). You'll have a fairly good project in getting your board programmed... and need a lot of patience waiting for configuration to complete,. I don't know of a reason why it can't be done. Sounds like a lot of work... but... sure beats "unsolder flash / program flash / resolder flash"... I only did the Spartan 3 programmer project because I told another questioner to this forum site that it could be done with minimal difficulty.. and later felt obligated to prove it.
  15. zygot

    FMC & SFP+ link (Aurora) on Nexys Video

    Perhaps this post should also go to the Sales or Suggestions area but it certainly is germane to this thread. I realize that Digilent's FPGA boards are not meant for commercial products. I also realize that, and understand why, Digilent might be loath to provide performance or test data for it's FMC connectors and transceivers where they exist. Since Digilent does its due diligence in testing these things it seems to me that making this information available to those considering purchasing a particular board for a particular purpose would be in the best interest of all involved. You're going to end up providing it anyway sooner or later though with perhaps some angst or unhappiness on the part of a customer who has invested time and money; time being the most costly investment. When a company can do something that's perceived as being honest, having the customer's interests as a priority, and generally just being a good partner then why wouldn't it want to do that. I don't see a downside to being considerate here.