zygot

Members
  • Content Count

    644
  • Joined

  • Last visited

  • Days Won

    27

zygot last won the day on December 1

zygot had the most liked content!

2 Followers

About zygot

  • Rank
    Prolific Poster

Recent Profile Visitors

4049 profile views
  1. My advice for driving a relay coil is the same. I'm not guessing about this I've completed designs. Doing some research is a good idea. So would be doing some simulations. There are free analog simulators available that will let you use realistic components.
  2. Do not try an drive a motor winding with a device IO pin that is not conditioned for such duty. Reactive loads will do nasty things to your device and subject it to conditions well outside its specified operation range. Your output pin must be isolated by a proper driver circuit.
  3. I forgot to mention the MAX11254 EVM. If you need a high resolution multi-channel delta-sigma ADC for low frequency applications this board is very usable. It was designed to be used in a stand alone mode via a USB interface or with the Zedboard; so it should work with either the Nexys Video or Genesys2 boards as well. There are a lot of options for using your own input signals. It has 50 or so jumpers to locate, which makes it flexible, but may make you cross-eyed for a few days trying to locate all of them. There just aren't that many pins in the FMC interface to trace through which is nice.
  4. I use the ATLYS Ethernet PHY all the time but I confess that I've never tried using it in 10/100 Mbsp operation. The Marvel 88E1111 is ubiquitous and unfortunately requires an NDA to read documentation about how to program it. Your problems could be related to register settings or perhaps failed timing paths. You don't mention a timing score for your routed design. This is where your debugging skills need to serve you. I'd start with a couple of debug ILAs ( one for 125 MHz and one for 25 MHz ) operation to try and figure out if the clock switching logic is failing. As you know the 88E1111 comes out of reset with its registers set to various modes depending on the state of a number of output pins. This information is freely available in the device data brief from Marvel. Are you resetting the PHY after switching from 1 G to 10/100? Have you tried putting the PHY into 10/100 before connecting to the switch? During debug I'd try to reduce the number of variables to a minimum. I'd start without using the switch and connect to a device with a known good 10/100 Ethernet port. It may take a while and some effort but you will figure this out.
  5. zygot

    Nexys A7 Reference Manual: SDRAM - Mbps vs MBps

    The convention for external memory data rate is on a per pin basis so the reference manual is correct. The peak data rate out of the external memory, as you surmise, depends on the width of the physical memory. If you have a single port (channel) external memory controller then a more important metric is how many bytes/s can you get out of the controller into your FPGA design. If you have a multi port controller vying for access to the memory then the peak data rate out of the external memory becomes significant. There are a lot of moving parts to trying to figure out if an external memory implementation will support any particular application as you likely suspect. There are a lot of factors to consider such as maximum DDR data rates for a particular device, memory burst length, and controller verses data clock ratio. [edit] I should also point out another possible source of confusion. Clearly the 650 Mbps refers to 'million bit per second'. Once you start talking about 'mega bytes per second' you'd be referring to million bytes per second divided by 1.048576. The hard disk drive manufacturers have been pulling our legs for some time by redefining the term megabyte to enhance the perceived capacity of it's products.
  6. zygot

    Prototype for thesis - tarjet selection, help!

    My first impulse would be to investigate a uC software solution for such a project; especially if your FPGA development experience is limited. I love solving problems with an FPGA but it isn't always the most sensible way to go. There are a number of inexpensive boards like the Raspberry Pi an adding a cheap interface of your own design could be fairly easy. Texas Instruments offers some cheap Piccolo DSP development boards and a nice software development platform. Keep It SSimple... or perhaps I should say keep the demonstration development as simple as possible so that you have the time to concentrate on making the demonstration as impressive as possible. [edit] If you have the skill and just want to do an FPGA based platform the CMOD can be easily be connected to a breadboard or custom PCB interface (Express PCB is one that I have experience with) supporting connection interfaces to all of the sensors and actuators that you need. Despite its deficiencies I still use my CMOD-A7 modules and just work around the issues. There are other inexpensive FPGA boards with a lot of IO as an alternative.
  7. @Matthew Cabral I guess that you didn't read my post about EVM/FPGA development board experiences. It just so happens that I did manage to cobble together a connection between the ADS4449 EVM and a KC705, so in theory you should be able to make it work with the Genesys2. I had to use a separate intermediary adapter between the EVM and the FMC connector. The EVM had support studs that I had to remove. The whole thing didn't end up being very mechanically sound. I had to supply additional supply voltages to the EVM. To repeat warnings that I've posted before , you have to understand all of the documentation carefully before making a purchase. The ADS4449 EVM is set up for narrowband (125 MHz) operation for signals centered around 185 MHz. In theory you can change components to change this. The data interface is simple enough but you need to implement a serial interface to set up the ADC. I just used the on board USB interface so that I could use the Ti software to set up the chip. You'll want to put the ADC into test data modes to verify the FPGA interface design. This board is a good example of surprises waiting the unsuspecting or knowledgeable user. I managed to do what I needed but can't recommend it to anyone. It was a lot of tedious work. Most high speed ADC evaluation board require a special baseboard which usually has an FGPA and accompanying software support. These things are usually geared to allow testing the performance of the device, not for use in a particular application. There just isn't many options for 4-channel high speed ADC equipped FPGA boards in a reasonable price range. One possibility for you might be: Cyclone V GT Development board ( 2 HSMC connectors ) 2 Terasic DDC boards ( each with 2 14-bit 150 MHz ADC and 2 14-bit 250 MHz DAC devices ) There are more ADC options in the Intel (Altera) world and Terasic makes a number of boards with multiple HSMC connectors. I have used the Cyclone V GT board with a DDC so I can confirm that they work together. You don't need such sample rates and in theory you could use one ADC to sample 4 channels sequentially.. if you understand the ramifications. On last warning. Asking what people think about possible compatibility of products is a good way to get into trouble. It's pretty easy to be well intentioned and provide bad advise or advise that's easy to misinterpret. Unless someone has actually had success with particular boards they can't offer useful guidance. [edit] Since I mentioned the Cyclone V GT development board I should add a warning to anyone deciding to purchase one. Some idiot placed SMT devices very close to the HSMC mounting post holes. The first time I connected a board to one of these connectors I sheared off on the these SMT ICs (part of the board JTAG chain) and had to wire around it in order to configure the board.... not a way you want to discover board features. For the record it's a very good and useful Cyclone V board...
  8. zygot

    Adept software Manual ... looking for author

    @Pavel_47 , I have no experience doing what you intend to do but I suggest trying the Xilinx community forums. Intel also has a similar venue. I figure that having access to the largest set of eyes is the best chance of connecting with someone who has helpful information.
  9. zygot

    Adept SDK C# Library

    In case anyone is unaware of this. DEPP is relevant to the older Digilent boards ( ATLYS, GENESYS) using the Cypress FX2 USB endpoint solution for asynchronous communication. All of their newer boards use (sigh!!!) FTDI USB endpoint devices. I suspect that the posted DLL is of little use to very many people.
  10. zygot

    Adept SDK C# Library

    Except for those posting here.... but one thing common to all who off advice, at any price, is that their efforts are likely to result in resentment rather than gratitude.... Unless it's on a scam topic... CMM Anyone?
  11. zygot

    Adept software Manual ... looking for author

    Hi @Pavel_47, I'm afraid that I still don't understand what your goals are. If you are interested in configuring FPGA devices Xilinx device documentation is excellent and there are application notes and a few demonstration projects. If you want to pass data between a configured device and a PC xc6lx45 recently posted a project showing how to do that using the BSCAN primitive. I can't think of other uses for JTAG. Designing a boundary scan system to do say, a complete PCB test, will require a bit more research. There is an open source JTAG effort that might be instructive. IEEE 1149 covers boundary scan.
  12. zygot

    Adept software Manual ... looking for author

    @Pavel_47, I've noticed a few of your recent posts and understand your frustration. Might I suggest that the Adept software isn't the only possible approach to using the USB resources. I've used the FTDI driver APIs with the Nexys Video and there's a very recent project posted to the Project Vault that's an excellent tutorial for doing what you appear to be interested in for the CMOD. Before venturing into specifics related to any USB device or API you have to have to have a good understanding of USB concepts and protocol. There are other resources for that.
  13. zygot

    VHDL: Why are those 2 variants not equivalent?

    Be careful with nested if..then..else statements. This structure implies priority. In ISE you can view the synthesis results in an RTL view to see a schematic of how it interpreted your code. Did you try an simulate the two variants? You haven't found a bug in either ISE or VHDL but figuring this out might be a valuable exercise. In VHDL the ':=' and '<=' assignments are not equivalent
  14. zygot

    busbridge3: High-speed FTDI/FPGA interface

    @xc6lx45, Well, thanks for the support. Again, it's a fantastic tutorial and highly usable. As I mentioned I intend to massage it a bit and perhaps add my own twist to the interface for a future project.
  15. I had intended to include these scope pictures: One shows the DAC waveforms after the first DAC packet updated the waveform buffers. The waveform buffers are initialized in the configuration bitsteam. The other shows the latency from when the ATLAS gets an ADC packet to when a DAC packet is sent.