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About zygot

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  1. zygot

    Eclyse Z7 and Vivado

    Short answer: yes. Long answer: The Zynq 7020 series PL and PS development tools, used on the Eclypse-Z7 and Zedboard, have been supported on the free versions of Vivado tools forever; no license required. Vivado will allow you to do anything with the PL that you could want. As to access to 'all features of the board" this depends on how much effort you are willing to invest due to the board design and supporting code and code distribution method. You can figure this out for yourself by using whatever version of Vivado. at least form 2019.1, you have and see if you can build th
  2. I don't know if this is relevant or not, but I have a number of FT232H modules that I've programmed for Synchronous 245 FIFO mode using the FDTI D2XX driver. I use the 'open by serial number' programmed into the EEPROM and don't have this problem using multiple modules in WIN10. I also don't allow WIN10 to automatically update drivers for anything that it chooses to. I realized that this still requires the user to use the dreaded FT_Prog application to know what the SN is. For years Altera/Intel had the same problem with the USB Blaster FPGA programmer application. Windows would always co
  3. One possibility is A Molex part from Mouser: Mouser P/N: 538-90122-0766. These are tinned on the PCB side and gold plated on the board-board side.
  4. If there's a path from the ROMs in the PL to the PS via an AXI bus then you can read the ROM contents; otherwise you can't. Such a path is a waste of a lot of PL resources. If your ROMs were dual port ram then that's different. You'd have to have a good reason for expending PL resources for that kind of architecture.
  5. Here's a snippet of my OCTAVE code used to create parts of the PhasorToy project that I posted in the Digilent Project Vault: clc; format long; fixed_point_format(true); # We want a sin lookup table covering 0 to (Pi/2) -1/(2^depth)-1) bits = 18; depth = 2048; rad_step = pi/(2*depth) deg_step = (rad_step/(pi/2))*90 max_rad = rad_step*(depth-1) maxdeg = (max_rad/(pi/2))*90 for i=1:depth sintab(i) = sin(rad_step*(i-1)); costab(i) = cos(rad_step*(i-1)); end # Create a scaled std_logic .coe file # Uncomment to write coe file # A better to do
  6. Whenever you create a RAM or ROM using FPGA vendor's IP you are given the option of providing an initialization file. The vendor has it's own format such as MIF. Don't use a csv format use the vendor's format. Writing a small Python script or C program to automate the process of converting an array of data to the MIF format isn't very difficult.
  7. zygot

    SPI slave in VHDL

    I don't want to lead, or mislead, you in your design approach. You should use either an external clock or MMCM/PLL derived clock for all synchronous logic in your FPGA designs. For your project you have a problem to solve if you want to use an SCLK input as a clock. Even if it is a derived clock it is not always running, and can have an inactive state of either '1' or '0'. As long as your system clocks are higher in frequency than SCLK it's possible to detect edges and phase relationships for the SPI signals. How you do this and what the requirements are for the system clocks and SCL
  8. zygot

    SPI slave in VHDL

    In FPGAs clocks are distinct and separate from logic signals. In your code you are clocking your process with a logic signal. This is not a good practice. You should clock logic with a clock signal. The tools do synthesis and place and route based on a timing analysis between clocks and the registers that are clocked. Your innerSCK makes for a poor clock in FPGA architectures and tools. If you have one of your SPI entities in one FPGA device controlling another SPI entity in another FPGA device this is a problem. In Xilinx Series7 FPGA devices clocks have their own routing resources and t
  9. zygot

    SPI slave in VHDL

    There's no good answer to your question because it depends on what your personal specification for an SPI slave is. You did start with that didn't you? For low speed SPI ( <25 MHz ) I've always used a 4x or higher local clock to derive or sample the SPI signals. This allows me to set timing constraints in the HDL rather than in the place and route. You don't have to do it that way. There can be reasons not to in fact. If your SCLK runs at 100 MHz and your logic is clocked with the same clock there are limited ways to detect certain conditions in real time. One possibility it to use mul
  10. You definitely need to use the Eclypse-Z7 and ZMOD timing constraints. You shouldn't get failing timing paths for the Digilent demos.
  11. As you've discovered, it's possible to try and simulate some designs over an unrealistic time period. Even if you were to try running a simulation for "60-80 hrs" ( I'm betting that you've underestimated the actual time due to OS constyraints) the amount of data generated would render normal simulation tools unusable for reviewing the results. Sometimes you can change the simulation resolution from ps to ns and speed things up. Sometimes you can work out ways to speed-up or bypass initialization periods ( DDR calibration is an example ) Sometimes you can't do any of these things. For video, re
  12. Why would you want to do try and do that when the board already has a USB port recognized by the tools?
  13. Ignore my previous post edit reference to board design validation for your project which is clearly a Verilog source... yeah, sometimes I wonder what it is that I was thinking too... I do want to point out that when you use the Xilinx IP Wizard you often get hard to find Vivado generated constraint files embedded into your project; like the Clocking wizard. If you specify an input clock frequency to the Clocking Wizard you will always get at least one timing constraint, that is the frequency specification of the MMCM or PLL input clock. If you also add a user constraint referencing the sa
  14. Yes, and @artvvbgave a reply that should resolve the problem. In this project you have two clocks. One is the MMCM input clock and the other is the derived 25 MHz output clock. Since you aren't using the input clock clk anywhere in your design there can't be inter-clock failing paths, or even inter-clock analysis. I've had experience with the board design tool for ZYNQ design get wrapped around the axle, so to speak, because I specified a non-integer PL clock in the Zynq System and made it an output to the PL only to have Vivado change the frequency assignment for the output pin symbol b