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About zygot

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  1. Then you shouldn't be supplying any transceiver pin location constraints. The IP setup specifies the MGT location and supplies it's own constraints. You should always look at any constraints that Xilinx IP creates to avoid duplicating or creating conflicting constraints in your toplevel constraints file. I still recommend that you work out ac/dc coupling issues based on the schematics for the Nexys Video and your FMC mezzanine board. Getting a bitstream and obtaining acceptable performance are two different things.
  2. @[email protected]'t seem to be inclined to respond to this question. Perhaps Dan personally, has developed a relationship with some one at Xilinx , but what exactly can he point to as a concrete example of something that has been corrected? After close to 30 years of using Xilinx tools I can write more than anyone would care to read about why I don't see a Reddit post as very worthwhile. But to save time I'll just present a recent experience. I was, for a couple of weeks, trying to get Vivado to use the correct PCIe MGT resources for a board the Digilent sells. No help from Digilent. I post
  3. So what do you have connected to those pins in your design? From the Nexys Video Reference Manual: "The gigabit transceiver lane includes a receive pair, a transmit pair, and a reference clock input to the FPGA, all going to MGT bank 216. The transceiver lane is wired to lane 3 (GTPE2_CHANNEL_X0Y7). The reference clock is wired to REFCLK1 of the same bank (GTPE2_COMMON_X0Y1). It is important to keep in mind that bank 216, being the only one available in this FPGA package, is shared between the DisplayPort source and FMC ports. Depending on the exact application, simultaneous usage of the FMC
  4. The AD9717 is a DAC designed for communications and waveform generation. It's not clear from you post if you want to create a static output or just limit the swing of a waveform. You've started off with the correct documentation, which is the ZMOD1411 Reference Manual, so read and understand that document as well as the AD9717 datasheet. To constrain the analog buffer output swing you have a few general options: You can limit the DAC input word to the desired low and high values that correspond to your output requirements. This approach basically uses only part of the DACs dyna
  5. I frequently instrument my FPGA designs involving a processor, usually a PC, in HDL using a counter. Obviously, you can clock a counter at any frequency to produce a reasonable resolution, what ever that means. But the real question is this: what does the concept of real time measurement mean to you? Resolution and accuracy are two different but related concepts. For a processor like a PC running Ubuntu or Centos there are a lot of variables that will affect any measurement. So capturing min/max elapsed times over longer sessions is likely to be more accurate than capturing one snapshot and
  6. I believe that I've managed to get the DDR3 memory working using Vivado 2020.2. It has to be a 2:1 clock ratio, 800 MT/s design. It's a shame that a DDR3 part with an 8-bit DQ bus was chosen for a board with four 1 GbE ports; but at least some local storage is available.
  7. @JColvin, Thanks for the information. I'm trying to see if the DDR works. It certainly doesn't do 1600 MT/s as 800 MHz is beyond the range of the -1 part clocking specifications. Oddly, Vivado will complain about an 800 MHz clock but will create a bitstream if you add a CLOCK_DEDICATED_ROUTE_BACKBONE constraint. Unfortunately, this is of little use as timing is so bad as to make the analysis useless. I haven't run into any information about anyone using the DDR on this board. I have no explanation for why the datasheet claims a 1600 Mbps maximum DDR rate for memory applications when
  8. I looked at the link and I didn't see what you saw; at least in the context of the information provided in your original post. Be careful of things that superficially look like what you want to do as an easy way to implement a project objectives. The problems appear in the details. But as I suggested before a simple thought experiment with some simple math is an easy way to see if what you want to do is even possible.
  9. No. I just visit the Digilent forums because I use their product and *trying* to help steering people with questions in the right direction is one way to take a break from what I'm working on. Well, possibly. If you can write your own AXI IP to DMA large amounts of data into the PS DDR. If you are going do do an HDL design it's a lot simpler to just transfer ADC samples into the DDR and DAC samples out of the DDR without having to add all ZYNQ complexity. I like simple when it's an option. I'd rather write one software application than 2 or more. I've found that the XEM7320 works well
  10. Well, if you advertise a product capability then anyone buying the product would expect that you are testing and verifying advertised claims. I suspect that the only thing being tested, if anything is, would be the Ethernet ports and possibly the PCIe interface. But it's not hard to prove that the published schematic is different than the actual board design schematic and that the QDRII+ memory works as advertised. Just make available the test code so that users can perform the test for themselves. If the advertised claims for this board are incorrect or untested then Digilent needs to do
  11. The place to start is with a bit of simple math. One ADC channel at 100 MHz Fs is 200 M bytes/s assuming that you don't compress 14-bit samples. Ethernet and USB are common PC interfaces. Neither can do uninterrupted data transfers. You can use FIFOs or some other local storage to accommodate gaps in the FPGA platform to PC communications but this requires careful analysis. You don't mention a maximum sampling interval if this is a one-shot process, or how long you expect to capture continuous samples if not. Storing even 50 MB/s of contiguous samples on a PC for any significant duration is no
  12. The NetFPGA-1D-CMT user reference manual states that it supports 1600 MT/s, or 1600 Mb/s per pin. This is consistent with the datasheet information for the -1 part for a 4:1 controller. The maximum BUFIO clock rate, according to the datasheet is 710 MHz, so I'm not sure how one gets an 800 MHz clock to the IOBs. Does Digilent actually test the DDR on the boards to verify its claimed performance?
  13. It's disappointing that the QDRII+ memory was botched and is unusable. I've tried to find a Mig project for the DDR... or any indication that anyone has ever used it. I haven't. When you do the board test, does that include the DDR? If so could you make available the MiG project settings? Is is possible to obtain test sources? The board would be very handicapped without any external memory.
  14. Xilinx has a few application notes for using the XADC feature of its Series 7 FPGA devices. Yes, it is complex. The first question to ask is what method of FPGA design flow are your using? Any answer will be different for HDL or block diagram flow.
  15. Xilinx has a few application notes for using the XADC feature of its Series 7 FPGA devices. Yes, it is complex. The first question to ask is what method of FPGA design flow are your using? Any answer will be different for HDL or block diagram flow. Ignore this post as it was intended for a different question and there is no way to delete it.