zygot

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  1. Usually, the JTAG chain runs through the FMC connector. Usually there's a way to bypass the FMC connector JTAG circuit so that it doesn't interfere with FPGA configuration. You only need to use the JTAG chain on a daughter card if there's something on it that you want to configure through JTAG. One more thing to learn about when connecting add-on boards to your FPGA platform.
  2. I assume that you mean a contiguous stream of ADC data samples. There's not a lot of processing that you are going to do on those samples with a Z7020 ZYNQ on the fly as data is being captured. If you look around on other areas of this site you can see how to capture 128 M samples of 4 ADC channels into DDR memory that can be processed on a PC later, using 2 ZMODs and a non-ZYNQ platform. The Digilent AXI IP isn't high performance or even good at demonstrating what a Z7020 and SYZYGY is capable of and I don't expect to see anything better. Is it possible to use AXI to DMA huge quanti
  3. I love happy resolutions to frustrating problems. Digilent could be more proactively helpful for basic customer issues. Perhaps a FAQ section or topical list of problem resolutions that customers could sift through on the web site? We all know that trying to update all documentation to keep up with problems caused by Xilinx tools version releases isn't feasible. But there has to be a better way, right?
  4. Most of Digilent's FPGA boards use an FTDI USB bridge device that can have 2 or more endpoints, all using one cable. One is used for JTAG and one as a UART. Vivado Hardware Manager communicates through the JTAG endpoint, so COM4 isn't what you are looking for. If you look under Universal Serial Bus Controllers in Deevice Manager you should see a USB Serial Converter show up when you plug in a cable attached to your board. The CMOD-A7 uses the same cable for programming and UART communications so a COMxx device will also show up. So how do you know what device goes with your cable? Look at
  5. Let's see if we can solve this. What OS is Vivado running on? Have you queried the OS tools to see if any USB devices get enumerated when you plug in the USB cables ( and for the Basys3 have the board powered on? ). For Windows this would be Device Manager ( usbview.exe is more helpful ) and for Linux it would be : dmesg | grep usb lsusb lsusb has command line options for more verbose replies. Vivado 2019.2 isn't the best version to use as it was the first time Xilinx abandoned the SDK tools and forced everyone to use Vitis. I still use Vivado 2019.1 for normal FPGA de
  6. I'm not exactly sure what you mean by 'program the port'. If you want to setup the internal DAC or ADC registers on one of the ZMOD pods you can use the low level controller(s) VHDL code that Digilent supplies in the vivado-library repo. These setup your ZMODs to function after power-on. You'll need some way to write registers in your HDL code if you want to change the default settings post configuration. You can use the USB DPTI for this, or you can add a UART interface to do this. If the preceding information isn't what you are looking for you'll have to be a bit more expansive in
  7. Why do you think that a soft processor ( or Vitis for that matter ) is necessary for your project? If you don't use MicroBlaze you don't need to use either the board design flow or any software development tools like Vitis. Your board is perfectly suited to an all HDL design flow. Just create a new project in Vivado and add all of your HDL source code, plus your constraints file(s). You can still use Vivado IP for clocking, internal storage etc. if that's convenient. FPGAs just aren't well suited for implementing replacements for general purpose computers systems. ( an exception mig
  8. Better yet, to get started, ditch the MicroBlaze and board design system altogether. Everything will be simpler. No mysterious signals added to your intended design. No hardware to export to the software development tools. No software co-design co-debugging. A good rule in engineering is to avoid doing things that make your work complicated and difficult. If you find yourself working for the tools, you're living in an unhappy universe. Make the tools work for you. The tools can't create designs, so don't allow them to dictate to you how you can do the design work.
  9. I've not used the USB104A7 nor do I use soft processors. I do use wrappers when targeting a ZYNQ device and using the board design flow to develop a basic ZYNQ system. After verifying and generating the board design I have Vivado create a wrapper file in VHDL or Verilog for the system. I make sure to uncheck the default setting when doing this and tell Vivado that I, not Vivado, will be managing the wrapper HDL. My top level entity instantiates the system wrapper as a module/component along with all of the other modules/components in the design. For ZYNQ designs the toplevel entity
  10. Wow, that sounds dangerous. FT_PROG is a utility for changing the configuration values of the EEPROM connected to FTxxx devices like the FT232, FT2232H, etc. If you aren't careful you can use it to render unusable random USB hardware connected to a root Hub in your PC that happen to be using one of those FTDI devices. Why would you want to do this to a part of your FPGA board that is responsible for configuration and UART communication? If you want to change the contents of a FLASH device connected to your FPGA FT_PROG is not the appropriate tool.
  11. If you look at DS180 Table 5 you will see a list of all of the Artix Device-Package options with HP IO Banks... none. @JColvinprovided the correct answer; that is trying to modify your Arty/CMOD ???? board to use one of the 1.2V standards is a bad idea. Perhaps you could provide a motivation for wanting to do this and someone could point you in the right direction to achieve your goals. If you really want an FPGA platform with an entire IO bank powered with Vccio = 1.2V you are better off buying a board that was designed to do that. There are UltraScale ZYNQ boards, like the Ultra9
  12. Well, as you can see those pins are not connected to anything. Some ZYNQ based FPGA boards have a PMOD or other connector connected to unused PS_MIO pins but your board doesn't. If you need a second UART you can export the unused PS UART to the PL though the EMIO and either connect the pins to PL logic or PL GPIO. JA or JB seem to be your only options for your board.
  13. Be aware that evaluation licenses are temporary.. so not very useful. What you are really paying for with FPGA vendor Ethernet IP licenses is the MAC code which all FPGA vendors provide only in encrypted form. Fortunately, you don't have to use the vendor MAC, or even any MAC for that matter.
  14. The addresses for AXI mapped peripherals are defined in the board design interface, if using that hardware design methodology. You can find all of the hardware design information in the SDK in the files that are exported to the SDK from Vivado; system.hdf and system.mss ( assuming that system is the name of your board design ). Unfortunately, the hdf file isn't readable in a text editor, but you can read it in Eclipse when the SDK is open.
  15. Ultimately, it's you the user. Yes, documentation can be confusing or have errors; and does so more often than anyone would like. When users run into these situations all that they can do is notify the vendor and hope that corrections are made. Never connect any external hardware to your FPGA platform until you've worked out the details to verify that there will be no nasty surprises. This is especially true when buying hardware from a vendor other than the one who designed and sells your FPGA platform. This is especially true when using external hardware that your FPGA board vendor doesn't li