zygot

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zygot last won the day on February 18

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About zygot

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  1. @sbobrowicz I didn't realize that my comments were "side chatter", off topic or even a waste of @dlgeng's time. I'm particularly disappointed in your reaction as I'd hoped that someone from Digilent would address the possibility of creating affordable FMC mezzanine boards when a potential customer mentions a need. I'd purchase an affordable GbE mezzanine card for my Genesys2 if you made one.
  2. I'm pleased that it isn't only me annoyed by this. Not too fond of the social media style "reputation" stickers idea. Since most of the comments are technical in nature having one's posting judged by people who may not have the technical experience is bothersome. As you point out this could become a means of retribution or even just a silly beauty contest. My vote is no rating. Ideally, all questions would get the perfectly correct answer by qualified staff; but we all know that everyone regardless of our knowledge can unintentionally fall short of that or even misstate a reply. Thinking of the less technically sophisticated it's hard for me to come up with a way to vet respondents before they write a post. If I realize that I've made a misstatement ( usually 20 minutes after the fact or the next day ) I make sure to post a correction. Really, I don't have any ideas about how to do any rating that's helpful.
  3. I would like to suggest that you abandon or at least rethink your ratings of people posting to this site based on the number of posts. I myself, find that I have been given a rating one might associate with a dizzying level of competence simply by passing the century mark in posts. On the other hand there are posters who clearly are superbly knowledgeable and labelled as a "newbie". I think that this is a disservice to everyone but especially those who lack the technical knowledge to ignore it. By the way, it's not that I consider myself to be on the low end of competency and expertise among posters, including those on the payroll offering presumed technical expertise. I would hope that the whole idea of rating people isn't a cynical sales choice.
  4. @dlgeng, This is wild conjecture on my part but I suspect that Digilent isn't the kind of operation to invest much money into in-house engineering. And, I doubt that you will find what you are looking for ( if you do please do tell...). Might I suggest that, given my previous post you and Digilent have a common interest? The biggest problem would be your time schedule. I would think that a GbE or XAUI LPC mezzanine board with an SPF+ connector would be a market opportunity given the alternatives.
  5. @elodg, Both of your posts have been very helpful and informative. If I were a product vendor using a common high density connector I'd want customers and potential customers to be apprised of level of effort that went into it's design. Frankly, I'm baffled at a vendor offering 2 not inexpensive FPGA boards sporting an FMC connector and not exploiting what's arguably both boards' best and most valuable feature. I understand the argument that Digilent can't verify every possible FMC mezzanine board but isn't it a bit short-sighted to put all that work into it and then act as if they don't exist? Is money really that tight that purchasing a few carefully selected FMC boards for test and advertising is beyond reason? Given the price point of Digilent products ( ignoring the occasional high-end "Net" FPGA board ) the overall capability of the Nexys Video and Genesys2, and the likely budget of their customers there really aren't that many FMC boards out there to choose from. For the most part FMC mezzanine boards are in a far more rarefied universe cost-wise than most Digilent customers likely live in.
  6. Sorry, You didn't ask about your simulation results or about issues getting the latest posted code to simulate. I'm done with trying. Don't you know anyone who's taken a first course in digital logic who might help you?
  7. By the way , the more you write the more convinced that you really need some help grasping the basics. VHDL was designed as a simulation language but was co-opted for synthesis because of its popularity. The language doesn't care about issues of synthesis but the synthesis tool sure does. A cursory reading of the syntax is not likely to be a helpful guide. With this in mind it should be clear that you can write perfectly fine VHDL code that can't be synthesized into something that works on hardware.
  8. Here's where being able to use a simulator might help. Your process is not clocked. Think about time, delay, storage and what's going on in your process. Simulate it and see what the simulator thinks of your code. I've already given you a broad hint in mentioning that I use concurrent statements and clocked processes ( OK in my state machines I use two processes, one clocked and one not...) I try and keep my concurrent statements and processes separate though sometimes this makes the code hard to read so I don't. I keep track of processes and signals associated with each clock domain using comments and keeping them together in the code. For the record it's entirely possible to have an whole design be combinatorial and not use a clock. I've had this as a work requirement for special purposes. Anyone doing that had better know what their doing and be very experienced if the design has any complexity at all; not for the inexperienced. You can shut me up for good by not posting your simulation experience or question related to getting a simulation working as your next post....
  9. D@n's reference "CE" as circuit enable has been bubbling up from my sub-conscience often enough for me to want to comment. CE is generally reserved to mean clock enable. I've run across people new to FPGA development with a strong background in ASIC development who get confused by the term. A clock enable prevents the clock source from making transitions. In the ASIC world there are clock sources with enables. In the FPGA world we imitate a clock enable with a signal used in our logic to prevent that logic from clocking under certain conditions. I re-checked the Xilinx HDL guidelines and didn't find any clock buffers with a clock enable. There is a clock control primitive but I've never had use for it. As far as I know none of the external clock modules used on Digilent boards have an enable. Well if that helps no one as least I can forget D@n's comment....
  10. @Digeng, You question raises an important issue about FMC connectors. The FMC connector, both the high-pin count and low-pin count versions, are used by the VITA standards committee and are covered by (I believe) the VITA.57 standard. As far as I know there's no law prohibiting use of a connector developed by a standards committee whether HDMI, USB, VITA, SATA or any other connector for a purpose other than the one involving a particular standard. I suspect ( I don't know as I haven't purchased the relevant standard ) that saying that your board meets VITA57 standards implies a level of performance for the transceiver IO. It may be that claiming to meet VITA.57 requires membership in that committee. I do know that some vendors specifically state that their FMC connector is NOT VITA.57 compliant. This seems to be a honourable and reasonable way to address this. When a vendor simply ignores the relevant standard it leaves its customers in limbo as to the motivation. I'd want to remove any such confusion if I were a vendor. I don't know what the topology of your cluster is. I don't know if you use GbE switches and require all the layers of XAUI or GbE. I am pretty well convinced that a bunch of Genesys2 boards might be candidates for such a project using the mDP connectors. You can look over the Transceiver Bootcamp project in the Project Vault if you're still reading this after my previous disclaimer. best of luck
  11. D@n, You write: "The FTDI chip creates two ports, but a driver on your system quietly suppresses one port and leaves you with a serial port that you can use". I've used the FTDI driver libraries and I take issue with that argument. The same FTDI USB device is used for both programming and as a UART and has two enumerations in the OS, one for the JTAG and one for the UART. It's not always easy to tell from Windows Hardware Manager which is which. There are some open source utilities that are a bit better at this. CMOD-A7 users should not have worry about things at this level (once they have figured out which UART port is the correct one). Both interfaces should be available ( assuming that your configured FPGA and a working UART interface ) when needed. FTDI has done some really stupid things to fight vendors of counterfeit "FTDI" components. They've released drivers designed to brick chips determined to be counterfeit and they've released released drivers that will create a multitude of non-existent enumerations making a headache for the user. I'm sure that neither of these relates to your problem but vendors using FTDI devices and people using products using FTDI devices should be aware.
  12. elodg, Seems reasonable. Can I suggest that you make the case to whomever it is that makes such decisions that providing this kind of information up front could enhance Digilent's reputation as a vendor in the market space that it live in? Even for your more technically "informed" and "sophisticated" customers there's only so much due diligence that one can do with a limited amount of published data. It seems that "Let the buyer beware" is the central core of US law ( I'm not a lawyer and don't provide legal opinions ) ( and this applies to purchasing products and services as well as selecting public officials...) and there are lot's of vendors who reply on that principal as a business model. Given that many or perhaps most of Digilent's customers are, from a technical perspective, at a heavy disadvantage in this regard might I suggest that Digilent set itself apart from those kinds of vendors by making a better effort at helping people make this analysis before a purchase?
  13. I forgot to mention that the power supply on the Genesys2 might need some analysis. I mention this as there was a user trying to fill the Genesys2 FPGA with a bit-coin miner design.... For close to the cost of the Genesys2 Xilinx has the KC705. I bought the Genesys2 for its HDMI and specifically for its mDP interfaces which happen to both be quite nice for my interests.
  14. In Windows 7 if I leave the Vivado Hardware Manager open after configuration and try to use the USB UART for an extended amount of time the USB device will disconnect. I've even had this happen when Vivado has been terminated. This seem to be a particular issue with Digilent boards having a similar JTAG/UART interface design.
  15. BeamPower, As Digilent supplies the demo they should also supply the assistance. Digilent and I have very different views as to what makes for a good product demo project.... If you look in the Project Vault I've supplied a few alternative demo projects for the CMOD-A7. I should point out that at least one of them requires a TTL serial UART/USB cable or breakout board because I've found that the on-board UART has issues. Fortunately, these alternate USB UART products aren't very expensive. Look at Adafruit and SparkFun to find a few varieties. I recommend that everyone ought to have at least one... and the nice thing about them is that, if you have HDL code for a UART, you can make any 2 IO pins be a UART. And Vivado hardware Manager doesn't think that it owns the interface and OSs don't detach the USB port after 30 minutes.