zygot

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zygot last won the day on September 21

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About zygot

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  1. It's occurred to me that even a 10 second lecture needs preliminary introductions. If you want to do cool stuff with logic then you need to understand numbers. Anything that you can do with decimal numbers you can do with binary numbers. Binary numbers can represent integer, fractional or mixed numbers; you just need to understand how to do the book-keeping that is required to know where the decimal point is in fixed length storage units like the std_logic_vector. You need to understand what happens when you throw away or truncate bits that don't fit your storage elements, and what happens when you use rounding to determine what that lsb should be. You need to understand bit growth for adding numbers and multiplying numbers. Once you figure out the basics your digital world becomes a vastly less limited place. Sure you can let others do your work for you using canned IP and such but this comes at a high cost and limits your horizons. It's not really much different for software applications, though these days few people would even consider trying to anything without pre-compiled libraries or high level functions that come with tools like Matlab.
  2. Do a little hunting around the Digilent forums...
  3. When adding HDL sources to a project you can add files from a particular directory or add copies into a new project. For IP generated by Vivado or ISE things get messy because the tools don't always specify source files relative to the current project. This can be irksome when you change the IP in a source project to fit the needs of a current project. Sometimes short-cuts have negative consequences. My advise is to re-create IP for new projects. It takes a little longer but you don't have to contend with surprises.
  4. zygot

    Clocking Wizard

    Where'd you get that idea? Spartan 3 devices have DCM blocks so it is certainly possible to create a 100 MHz clock from a 50 MHz input. You are of course using ISE since Vivado doesn't support older devices. If you don't find what you are looking for in the IP you can always instantiate a DCM as a macro in Verilog ro VHDL. Sometimes, like the Genesys Vritex5 it's not obvious from the selection of clocking IP how to get what you want. The solution is to learn about the device and instantiating resources as macros from the literature.
  5. First of all the Project Vault is a place to post working projects, not ask questions; so this post belongs somewhere else. Doing things and knowing how they work are often two different challenges. Understanding how to create a tone and how to implement LTE are worlds apart. Wanting to understand the concepts for both are worthwhile goals. I'd advise starting with a good textbook. Janak Sodha's book Fundamentals of Communications Systems is a good introductory text with lots of accessible examples. Analog Devices has a number of good application notes texts available as well. Beware that there is a lot of math involved. Fortunately, one doesn't have to do brute force math to implement basic signal creation. To start, consider a vector. It has length and an angular orientation relative to some X-Y coordinate system. If you pin the tail to a fixed point and spin the head of the vector around at a constant rate you've created the basis for a tone. The basic building block of a tone generator is the phase accumulator. The phase accumulator is nothing more than an adder where you don't care about overflow. The time it takes between overflows represents the tonal frequency. Of course tones are sinusoidal so the actual tone requires using the accumulated phase as a pointer into a sine or cosine lookup table. And that's the 10 second introductory lecture on communications. Now if you suppose that creating a tone and creating the exact tone with the qualities that you want might be a bit more complicated then you assume correctly; but dealing with the details isn't a 10 second presentation. Now, you can do all sorts of interesting things with your rotating vector like modulate ( vary ) its magnitude for AM. Or, instead of changing the phase input to your phase accumulator at a constant rate you can modulate the input to do FM or PM. If you create a number of different tones and add them you can encode information that can be extracted by finding which tones make up the signal. There's quite a leap from there to modern communications in terms of what you need to understand but that's the fun. All of these can be implemented in FPGA logic with a lot of knowledge and a bit of insight. Communications is little more than creating and manipulating tones with some sophisticated conditioning involved. Conditioning is important because poorly designed or constrained communications interfere with other even well designed communication systems. That's why the experimenter needs to be careful building hardware that transmits signals. Drowning out an FM station that you are listening to while playing around with your hardware might be fun for you but will not be so much fun for your neighbours; particularly if they are dependent on a communications system like police and firemem or pilots. The pioneers of modern communications were mathematicians like Fourier, Laplace and Euler who understood the basic concepts long before other very smart people got around to playing with tonal generation for transmitting and receiving information. And all of it is possible because someone had some insight that made the very difficult practical to implement.
  6. You don't mention what board you are using, but really it doesn't matter. Just because a header has 2 pins next to each other doesn't mean that they are suitable as differential inputs. For inputs what really matters is what logic standard is driving your differential signal. But even if this is from a 3.3V differential source that doesn't mean that you can use any particular connector pins to receive the signal. Trace length mismatches between the + and - can easily create big problems. In theory you can add termination allowing FPGA pins on 3.3V powered IO Banks to receive 2.5V differential signals but since the termination will be some distance from the actual FPGA balls and not likely to have good signal integrity properties I'd advise against it. Your best bet would be to create a small board that plugs into your PMOD and converts the differential signal into a LVCMOS33 compatible single-ended signal; assuming that you have the know-how to do it. I assume that if you did you wouldn't have submitted the question. Depending on the data rates it might be possible to just use the + or - signal; again assuming that you properly condition it to be 3.3V logic compatible.
  7. I don't have the Arty Z7 board so I've not used the ULP TUSB1210 on it. I might have some helpful answers. First of all the TUSBxxx On-the Go USB devices are almost always connected to the PS where drivers can handle the functionality that is missing in the device hardware. Looking at the schematic for your board this is the case for you too. There are no constraints for PS IO pins as the hardware is not in programmable logic ( the PL ) and can't be reconfigured. For FPGA pin connected to programmable logic IO banks you can certainly append multiple constraints like location, IOSTANDARD, Drive Strength, etc onto one line. Usually, these get long enough so I've never tried appending timing constraints. Timing constraints can get messy all by themselves. I prefer maintaining the constraints file myself rather than have Vivado or ISE do it and often have to add one that I don't know, or more likely can't remember, the syntax for. There's a whole user manual for constraints that is isn't always helpful. It never hurts to start with the documentation but sometimes trying to get a specific answer is frustrating so I'm not shy about finding alternate means. After place and route you can open the Implemented design and view the pin constraints in the I/O Planning view. From there you can select a new constraint or change a default one and let Vivado show you the syntax; just let Vivado ammend your existing constraints file. A similar process helps figure out timing constraint by using the Edit Timing Constraints tab or in the Timing Analysis View. Sometimes, I have to work to figure out how to set reasonable timing constraints that result in consistently good designs with very low or 0 Timing scores.
  8. The Nexys Video is a -1 part with maximum LVDS rates <= 950 Mbps ( less than the ATLYS Spartan 6 board ). LVDS is a 2.5V or lower standard and TMDS for HDMI is 3.3V so you'd expect data rates to be higher for lower voltage signalling. For educational purposes and home projects this doesn't mean that you can't achieve data rates at toom temperature above this for any specific design. For commercial projects or professional projects it's wise to observe the AC switching specifications for your part. Data sheet specifications are guaranteed and **tested** performance numbers. You might be lucky and get a device that performs near the point where some of the specs might have made it to the next speed grade but don't count on it. Saying that a board works fine for out-of spec designs is one thing; hooking up your board running the applicaiotn to professional grade measurement tools and citing actual properly made measurements is another... not that I'm saying that hamster is wrong. **tested** is something that needs to be researched carefully and probably doesn't mean wht you think it means.
  9. I've recently added two more boards to the list of DUTs that this tester works with. When Intel announced the Cyclone 10 family and I realized that instead of making the Cyclone family a better product it was an opportunity to further fracture Cyclone devices into more low end and less useful products and push customers into paid tool subscriptions (Cyclone 10 GX) I lost interest. I did recently get the Cyclone 10LP development board for a project ( there's not much out there to choose from so I must not have been the only one to lose interest ). The part is a really small device with minimal resources but the board has an 8 MB HyperRam, a 1G Ethernet interface and reasonable IO for $99. Hmmm.... this board would make a nice optical sensor video server using one of Terasics' add-on boards. I've had the MAX10 Development Kit for about 2 years now and spent quite some time trying to implement the Ethernet interface ( it has 2 1G ports! ). MAX used to be a PLD but these days looks more like a Cyclone without full IO support. I put the board on the shelf but decided to give it another whirl having ported an Ethernet PHY DUT so easily for the Cyclone 10LP board. This time things went smoothly though Quartus is doing some magic that isn't obvious to anyone trying to do the same thing from scratch for the device. The device on this board is quite large, there 2 1G Ethernet ports, an HSMC connector and DDR3 external memories. The price is about 2x the $100 I associate with cheap usable FPGA development platforms but it is quite capable. There are a number of options here for anyone wanting to do something with 2 100+ MHZ ADC/DAC channels on a tight budget. It would for sure be nice if I could find an equivalent Xilinx Series7 board for either of these.
  10. Well you are partially correct. There certainly are differential logic standards for 3.3V logic. Decades ago 3.3V IO was the cutting edge and differential logic has preceded FPGAs by decades. But not since the Spartan 3A have any Xilinx devices that I can think of supported a differential IOSTANDARD for IO Banks powered by 3.3V Vcco. It is possible, though arguably not practical, to add termination allowing differential reception, in a board design. The question is why would a company continue to put such connectors onto their boards, in the face of Xilinx documentation to the contrary, after having been called out by customers, without ever providing a PMOD designed to use it, basically wasting up to half of the IO pins provided on their development boards, when an suitable alternative is so trivial to implement. Why would an FPGA vendor put up with a partner subverting students and customers from learning how to use their devices in all of their glory? Why ponder questions that will never be answered? If you want to experiment with LVDS or differential IO on an FPGA find a board that is designed to let you do so. Finding such a board is a question for which there are answers.
  11. Most connectors have very short insertion cycle specifications; unless they are expensive and specifically made to endure a high number of insertions. Having made that statement I will say that I have to maintain at least 4 tower and 2 laptops to support all of the obsolete tools and drivers that I've accumulated and still need; and I have yet to identify 1 USB port that has gone bad. My main Win7 delvelopment PC is as old as, well.. Windows 7 is. It's not a bad idea to invest in a few USB hubs. They are a lot cheaper than PCs. There are reasons for doing this even if you aren't worried about connectors going bad. I recently destroyed ( well I haven't bothered to take the time to figure out what the problem is ) a USB HUB while developing a FT232H project ( this is a lot easier to do than you might think) ; glad that it wasn't one of my motherboard USB Host Controllers... I generally keep USB cables plugged into development boards when not being used. I've had a number of USB connectors rip off of such boards. In particular, if you have any development board with a USB connector lacking thru-hole shield ground tabs I guarantee that sooner or later it will come off with the end of your cable. One way to mitigate this is to apply some epoxy around the connector before using such a connector. I do this as a habit. I've found that most USB micro or mini cable connectors require a high insertion force, and that's if you are trying to plug it in correctly; some are worse than others. Zygot rule for the day: "Break cheap stuff, not expensive stuff". Corollary: "You are going to break something sooner or later". [edit] I should have specified that by USB HUB I mean self-powered USB HUB.
  12. Well I think that this is better stated as saying that most serial terminal applications can only connect to one COM port at a time. It is possible to mave multiple UARTs in your FPGA design and connect to multiple serial terminal applications. I like Putty myself, but there are other options. Another possibility is to look around in the Digilent Project Vault and see at least 3 project with source code that might accomplish what you want to do. If you instantiate your own UART you can access any number of internal registers or memory.
  13. Again, making the customer resolve you design issues is not nice. Especially since many of your customers aren't experienced electronics design engineers. So you have a particular 100 nf capacitor in mind? Did you use a low ESR cap? What was the part number? When your all-thumbs customers destroy their board trying to implement your "fix" are you willing to replace those boards? I have a lot of FPGA development boards from Digilent that use the same USB cable(s) as the CMOD modules do. All of these have a separate power supply connector and JTAG header so the boards are usable without a USB cable. Curiously, the only product with an issue, happens to be lacking either a power supply connector or a JTAG header and is therefore unusable without a USB cable and that's the one that you don't sell with a cable. You've even refused to recommend a cable for customers. Since the issue was first raised Digilent has only provided fuzzy, non-specific solutions which doesn't engender confidence. Really, please stop marking these "answers" as a solution to the problem. If the problem is the cable start selling the modules with a cable and then declare the problem solved. The solution is either incredibly easy ( you supply the cable ) or needs a re-design. Either way your customers can't be expected to do your engineering for you or even find "good" parts such as a cable on their own. Digilent, can on the other hand resolve the issues completely; they just have to want to. By the way I've never come across a "bad" cable though I have no doubt that there are vendors selling such things.
  14. Well, since this keeps getting batted around, after years of customers reporting problems, I'll just repeat what my situation is. I have 2 of the earlier CMOD-A35T modules. I have a drawer full of micro USB 2.0 cables that I got with many FPGA development boards. Whenever I use one of the CMOD modules for a project I just randomly select on of the unused USB cables. I've never had an issue programming either of the modules using either Vivado Hardware Manager or the Adept Utility for Windows. I consistently have an issue with the USB endpoint getting detached when the board is configured and Vivado Hardware Manager is running such as when trying to use the ILA functionality. I also have a similar problem with Vivado Hardware Manager running while trying to use the COM endpoint with another application such as Putty. I've stopped using the USB cable UART functionality and now use a TTL USB UART cable or breakout board and spare IO pins. I now just create my own debugging functionality to replace the ILA. The CMOD is the only FPGA board that I need to make such accommodations for. Are there bad USB cables out there? Sure. Could Digilent have resolved this issues years ago by just providing a cable with their boards? Maybe. Note that the smaller cheaper FT2232 devices have fewer ground and power pins than the older devices in larger packages. I doubt that issue is resonance (EMI) related. I haven't seen any indication that there is a general issue with any of my designs requiring too much power ( or more importantly too much instantaneous power ) than the USB 2.0 specifications delivers; but I also don't pretend that these modules are just like normal sized boards except smaller so my designs are appropriate to expectations. There's no doubt that using an FPGA board that can only be powered through a USB 2.0 cable is problematic; for a number of reasons. Personally, I suspect that the board stackup design is more of an issue. There just isn't a lot of mass to these things. From my perspective there likely is a driver issue involving Vivado hardware Manager and VCP. I can say that things on the Intel side with it's JTAG/COM enumeration are a lot worse. I don't think that FTDI planned on the success that it would have when it created it's first multi-endpoint devices. Adding a capacitor for bulk storage will certainly help if the issue is an inability of the USB upstream port to deliver instantaneous current requirements. This would be, in general a design specific phenomena. Can users create a design for the 35T that requires more than the 500 mA USB current provided? Almost certainly. The CMODs just aren't tiny ARTY boards. By the way the most recent thing I did using the CMOD-A735T board was last month for my post on SOC Strategies. This involved hooking up an FT232H in Synchronous 245 FIFO mode with average data rates > 40 MB/s so my designs haven't all be simple low speed ones. I can't for the life of me figure out why I need to be repeating myself once again. This issue has always been simple to resolve ( assuming that cables are an issue ) and that is for Digilent to take responsibility for it's own products and supply cables that work. So the imaginary cost is a bit higher. The real cost to the consumer would be lower as I'm sure that Digilent can buy cables in the 1K lot cheaper that users can buy individual cables. Now this isn't just a Digilent problem as everyone seems to be supplying products without required components in order to create a false impression of the actual cost of the product. You can buy a Raspberry Pi 4 cheap, but by the time you get the non-standard power supply and HDMI cable, and Micro-SD card in order to actually use the thing your costs are twice what you paid for the board. Vendors.. stop it already! Making problems created by vendors bad decisions a customer problem might seem to be the easy path but it's really a bad idea on very many levels.
  15. Terasic has the C5P board with the largetst Cyclone V GX device and 4 lanes of Gen 1 PCIe. The significant aspects of this board are the low price ( for an FPGA board with PCIe ) and the Terasic provided PCIe drivers for Linux and Windows. To my knowledge this is the first reasonable cost solution for doing FPGA development with a PCIe interface not requiring any third party IP or drivers. I've been using one for a couple of weeks now and am impressed. I've built both FPGA designs and PC applications using free tools. If you really need to develop an FPGA centric project with a high speed PC interface and don't want to bother developing your own USB 3.0 code (4 lanes of PCIe Gen 1 have data rates that are a good deal faster than USB 3.0) I suggest looking into this board. The C5P started out as a stand-alone board but now is connected to Intel's OpenVino Deep learning initiative. My only complaints so far are that it took so long for one of the big FPGA vendors to allow such a platform to be available to developers with a small budget; and that there is no similar board for those of use who prefer to use Xilinx tools and devices. I have used similarly priced boards from Microsemi and Lattice but you need a licence for the tools and the drivers are limited.