zygot

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  1. Yeah, but now that you know how to do it the next time will be easy. I strongly encourage using the XADC for all more serious Series7 projects, fan with heat sink, heat sink without fan or nothing at all. If you don't check on things you are just operating on assumptions. In electronics ignorance is rarely bliss ( for long ), especially of you are pushing your hardware. I kind of agree with you that LUT52% FF68% usage, with minimal or no IO being driven ( I assume ), and clocked at 200 MHz shouldn't cause your platform power supply to roll over and play dead... but that's the nature of th
  2. Since you are using the ATLYS I feel that it's appropriate to warn you about those USB Type-B plugs. The only thing holding them onto the board is a thin strip of copper on the mounting surface of the PCB. I've had about a 50% failure rate with these over repeated use; that is the connector, and copper signal traces being ripped off the board. One problem is that some of these have a fairly high insertion force requirement and the surface mount USB connectors just aren't up to the task over time. It isn't only cheap FPGA boards with the problem. I have a couple of 'not cheap' nVidia dev boards
  3. It's kind of a shame that Digilent was historically so sloppy with their PMOD designs on the FPGA boards. Very few PMODs are connected to clock capable pins on the FPGA. A problem is the 12-pin connector... it really limits what you can do with it, and I think that the decision to double the GND and Vcc pins is generally not all that useful and certainly exacerbates the issue. A simple PMOD with holes for an external clock module would make the whole ecosystem better... but what's the point when almost none of the FPGA boards can make use of it? I strongly advise Digilent to reconsider th
  4. TMDS requires 50 termination to function. The HDMI INput connector J3 uses the TMDS141 TMDS re-timer device to accomplish proper termination. You need to be careful with HDMI. Because of those 50 ohm terminators you end up with a path for external devices to pump current into the ATLAS Vccio rails... so the system power-up sequence is important. You don't want to drive current into the FPGA rails before the ATLYS board has been powered an it's own power rails are stable. Just connecting supply rails between two independently powered boards without carefeul current management is scary. Ide
  5. That's a tall order. Digilent made a few breadboard cards for the VHDC connectors on the ATLYS and original Genesys boards but they aren't ideal. I think that your best bet is to use the PMOD connector and make your own external clock module card. If you go to Mouser (or convenient distributor for you ) and search for "74.25 MHz clock module" you will find a few 3.3V single-ended modules available. This would be the simplest way to go. Fortunately, your frequency isn't odd so there are possibilities. For sing;e-ended clock inputs you'll need to use the _p pin. The only peripheral for
  6. No. Timing constraints help the synthesis and P&R make good decisions about routing and placing logic, it can't magically select the best clocking scheme for you and implement it. You can make a large number of DMC clock output frequencies from a given clock input frequency; the impacted variable is jitter. The ISE and Vivado clock wizards allow you to specify output jitter, so you can increase the odds of getting a frequency close to the desired one by relaxing the jitter spec. You can also just instantiate a DCM as a primitive and choose your own multiply/divide factors. This approa
  7. One of the more glaring deficiencies of the Eclypse-Z7 is the lack of SMA clock input and output ports. For such a platform this is huge blunder, at least as far as customers who use it are concerned. One problem for the Eclypse-Z7 is that it competes with the new "PRO" version of the Analog Discovery, which depends on 'added value' ( i.e. engineering $$$ ) to justify it's price premium. This type of conflict generally doesn't bode well for the cheaper general purpose platform.
  8. I like the idea of cascading DCMs. You will not get ISE or Vivado Wizards to evaluate you own IP, so you will have to do this for yourself. I don't think that the Wizard even knows about cascaded DCM designs anyway. You might be able to get an idea of the feasibility of your concept by trying to use the Wizard to create your clock outputs from the given input clock and see what it produces. Unfortunately, while the Spartan 6 device is still a great device it has inferior clocking capabilities than the more recent Series 7 devices. Getting an arbitrary clock out of any input clock can
  9. Well, no. A 12-pin or even 6-pin PMOD cable would violate the 2nd tip: Don't connect Vcc rails between boards. They are fine for PMODs because the add-on boards need Vcc. It's very easy to create big problems with cabling; you have to verify that the cabling is connecting the proper pins together, and nothing else. For 1 MHz signals it's probably ok to use flying leads. You can buy 6" leads with female-female headers, male-female headers or male-male headers from places like Adafruit. You want male-male wires. To be safe you might stick both ends of a male-male lead into each of the mating PMO
  10. Xilinx installs the Document Navigator when it installs the tools. Before trying to use a device, or a board, or even the tools you need to download and read the documentation pertinent to your hardware and how to use the tools effectively. The answers to all of your questions are available if you look for it in the proper place. This is how someone with a lot of experience using FPGA tools would prepare for starting a project with unfamiliar hardware. Trying to solve problems as you run into them by posting non-specific questions is simply a very bad idea...
  11. Reading the current version of the on-line reference manual for the Genesys ZU-3EG I found this: "Attachment detection is implemented by the Platform MCU and pod presence is communicated to the MPSoC over the SYZYGY_DETECTED signal. For now, it is up to the MPSoC to read the port's SYZYGY DNA and implement SmartVIO functionality by requesting a compatible voltage on the VADJ rail. SYZYGY DNA is accessible on branch 5 of the I2C multiplexer on the main I2C bus at address 0110000b." That's not a lot to go on. The details of the current state of the SYZYGY support that Digilent provide
  12. Yeah, I sometimes get sloppy with some projects. But here's a different way to think about making the best use of your very limited time; it's one that I keeps getting thrust into my mindset by complicated projects. For 'side' projects this is all about self-preservation and self-defense. Spinning my wheels is more frustrating than forcing myself to do some sort of code version preservation. There are no hard rules and you don't need versioning tools. Just zipping up a project when you know that there are going to be major changes is often sufficient. Developing some good, simple, habits and p
  13. I thought of something that I forgot to mention. The standard PMODs are good for low toggling rate interfaces. Also they have 200 ohm series resistors that, to some extent, help protect from ESD and shorts, both temporary and long term, and to a lesser extent transmission line issues. Even still try and keep cabling as short as possible, especially with flying leads.
  14. I don't have access to your hardware but SYZYGY requires a DNA handshaking session between the carrier and POD MCUs prior to enabling the power supply for the POD. That would be the first thing to check. Since you have two copies of the same board it should be possible to see what's different about the initialization. process.
  15. I've done this many times. What boards are your using? Tips: make sure that you have a good bonding of the GND reference for both boards, especially for single-ended signals. PMODs have 2 GND pins. Don't connect any power rail of both boards together Before configuring both boards as a connected system take extra precautions to be sure that your have assigned the pin locations correctly; that is check the post route pin assignments. Make sure that there is no possibility of contention. The pin on the sink side should be an input only and the pin on the source side should