Foisal Ahmed

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  1. Hello, I have bought many basys3 boards of Xilinx Artix-7 FPGA of device xc7a35ticpg236-1L. My previous FPGAs of the same model where the QSPI was manufactured by SPANSION and programme can be easily downloaded on that configuration memory. But QSPI flush memory of new basys3 of the same model is manufactured by MXIC and I could not able to download my program. In Vivado 2015.1, I could not find any configuration memory that can be used to be programmed. Thanks in advance for any idea to solve this problem, regards, Foisal
  2. @xc6lx45 Thanks again for the reply. At a time one oscillator is activated. What do you mean by injection locking?
  3. Dear xc6lx45, Thanks for your reply. Actually, my main concern is why the upper row and lower row in the layout showing significant higher frequency or lower delay than the adjacent row of the layout. I don't know actually whether the top row or bottom row of the layout is out of specification or not. So far, my designed ring oscillator meets the time specifications, as well. Looking for a more specific answer. Please find the attachment file for the figures what I actually wanted to say. Thanks, Foisal
  4. Hi, I am using Xilinx Artix-7 FPGA of device xc7a35ticpg236-1L. I made 7 stage ring oscillator using LUT-6 to observe the frequency of the various locations in the layout. The problem what I have found that the RO showing more higher frequency in the top row and bottom row of the layout than other row position. I have checked various position by row-wise. It is usual that all location has little difference to other adjacent position due to having some technological process variation. But the difference between the top row of the layout and the adjacent row is around 10MHz. However, the usual difference is around 0.5-2 MHz. Thanks in advance for any comments and reasons. Regards, Foisal
  5. Dear hamster, Thank you for your reply. It makes my intuition clear. regards, Foisal
  6. Hello, I have a very simple technical question. In Xilinx xc7a35ticpg236-1L Artix-7 FPGA there have only 20800 LUTs found both manual and vivado tools showing also. But in the layout or floor plan, the number of LUTs is more than 20800. Each LUT in the layout plan can be accessed by changing the location through XDC file. But why all LUTs( which is more than 20800) in the layout could not be implemented at a time. Is there any physical constraint? Thanks in advance. Regards, Foisal
  7. Dear jpeyron Thanks for your feedback. I think this might be helpful. Regards Foisal
  8. Can anyone give me the information about the Core voltage of Basys3 Board of the FPGA chipArtix-7, XC7A35T-ICPG236C? How can I change the core voltage to accelerate any operation? Thanks in advance. Regards, Foisal
  9. Dear D@n, Thank you for your nice technical information. Actually, I want to observe some aging effect on the LUTs by giving them some electrical (DC0 or DC1) and high-temperature stress. I have already got some data where I have implemented a benchmark circuit on the particular area of the FPGA and applied that stresses on the FPGA. Since then, I have taken frequency by ring oscillator to observe the aging condition of the benchmark part and other unused parts. Before giving stress I have taken frequency from all the LUTs of the FPGA. However, the problem what I found that after aging not only degraded the used part but also degraded significantly other unused parts where there was no benchmark component during the stress. Actually, my assumption is that the aging mechanism also worked on the other unused part due to the initial value of the LUT 1'b0. You know Inside LUT, there is CMOS circuit and if the initial value is 1'b0 then aging mechanism NBTI is occurring automatically when faced with high temperature. That is the main reason why I want to force all LUTs /register initial value 1'b1 during power-up so that aging effect only occurs in the specific benchmark circuit area. Previously, Xilinx had some direction in this regard using ISE version but I am using Vivado tools. Please see the below Xilinx link: https://www.xilinx.com/support/answers/3123.html https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/destech/html/cd_webpackcontrolling_register_initial_states.html Sorry, I do not know whether my explanation and query are understandable or not. Actually, It will be better for me to know how to give constantly DC Logic 1 stress on to all LUTs of the FPGA. Thanks and regards, Foisal Ahmed
  10. Thanks, BogdanVanca for your reply. The default initial state for all registers, LUT and latches are zero (Logic state 0). Before downloading the specific Verilog file on the FPGA, I want to force the initial value of all LUTs as 1 (logic state ) instead of the default 0 value. So, Where and how I can do this. Please help to solve the Problem. Thanks
  11. I am using Vivado 2015 tools for Basys 3 FPGA Board. I want to fix all of the Register into default Logic state 1. Where and how can I do this? In the Tools or XDC file. Please kindly solve this problem. Thanks for advance. Regards Foisal Ahmed
  12. HI @JColvin, Thanks a lot for this valuable link. In the problem, I have another problem after analyzing that the above problem only shows when I have changed XDC file by manually. To take ring oscillator frequency every time I have to move LUT location changing like BEL, slice etc. Some location does not reset but some location resets automatically. Besides these, In my design have some timing slack which I have not removed yet. Thanks Foisal
  13. HI @jon Is there any tutorial how to use it? Thanks Foisal