Foisal Ahmed

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  1. Dear elodg, Thanks a lot. This is the answer what was I actually anticipated. One more question @elodg, what is definition of nominal voltage/ values? Thanks in advance. Regards, Foisal
  2. Hi everyone, Regarding the above post i need some other queries. Basys3 board has option to use external power supply changing JP2 jumper and externally using J6 port 5V dc can be supplied. The range of extrenal voltage is 3.6V to 5.V. According to the basys3 manual regulator circuit (IC10: LTC3633) is used to provide 1V for FPGA core. My question is that if I varied this external supply voltage in the basys3 board, whether the core voltage (1V) of FPGA is chaged or not. For example, If the external supply voltage of the board is changed to 4V , what will be core voltage of FPGA? Tha
  3. Dear JColvin, Thank you for your nice explanation. Actually, i do not want to increase the speed of the operation. Instead, I like to want vary the supply voltage below 1.1V by using externally DC supply voltage. Some, research using Spartan-3A FPGAs in Numato Lab FPGA development boards (https://numato.com/product/elbert-v2-spartan-3a-fpga-development-board) where they vary input supply voltages from 1.1V to 1.40V. I just want whether it is possible or not of doing this type of things using my Basys3 board. Best regards, Foisal
  4. Hi everyone, I am using Basys3 Board of the FPGA chipArtix-7, XC7A35T-ICPG236C. How can I increase / change the core voltage of the FPGA to accelerate any operation? The nominal core voltage is around 1.1V. If possible plz. show it graphically. Thanks in advance. Regards, Foisal
  5. Hello, I have bought many basys3 boards of Xilinx Artix-7 FPGA of device xc7a35ticpg236-1L. My previous FPGAs of the same model where the QSPI was manufactured by SPANSION and programme can be easily downloaded on that configuration memory. But QSPI flush memory of new basys3 of the same model is manufactured by MXIC and I could not able to download my program. In Vivado 2015.1, I could not find any configuration memory that can be used to be programmed. Thanks in advance for any idea to solve this problem, regards, Foisal
  6. @xc6lx45 Thanks again for the reply. At a time one oscillator is activated. What do you mean by injection locking?
  7. Dear xc6lx45, Thanks for your reply. Actually, my main concern is why the upper row and lower row in the layout showing significant higher frequency or lower delay than the adjacent row of the layout. I don't know actually whether the top row or bottom row of the layout is out of specification or not. So far, my designed ring oscillator meets the time specifications, as well. Looking for a more specific answer. Please find the attachment file for the figures what I actually wanted to say. Thanks, Foisal
  8. Hi, I am using Xilinx Artix-7 FPGA of device xc7a35ticpg236-1L. I made 7 stage ring oscillator using LUT-6 to observe the frequency of the various locations in the layout. The problem what I have found that the RO showing more higher frequency in the top row and bottom row of the layout than other row position. I have checked various position by row-wise. It is usual that all location has little difference to other adjacent position due to having some technological process variation. But the difference between the top row of the layout and the adjacent row is around 10MHz. However, the
  9. Dear hamster, Thank you for your reply. It makes my intuition clear. regards, Foisal
  10. Hello, I have a very simple technical question. In Xilinx xc7a35ticpg236-1L Artix-7 FPGA there have only 20800 LUTs found both manual and vivado tools showing also. But in the layout or floor plan, the number of LUTs is more than 20800. Each LUT in the layout plan can be accessed by changing the location through XDC file. But why all LUTs( which is more than 20800) in the layout could not be implemented at a time. Is there any physical constraint? Thanks in advance. Regards, Foisal
  11. Dear jpeyron Thanks for your feedback. I think this might be helpful. Regards Foisal
  12. Can anyone give me the information about the Core voltage of Basys3 Board of the FPGA chipArtix-7, XC7A35T-ICPG236C? How can I change the core voltage to accelerate any operation? Thanks in advance. Regards, Foisal
  13. Dear [email protected], Thank you for your nice technical information. Actually, I want to observe some aging effect on the LUTs by giving them some electrical (DC0 or DC1) and high-temperature stress. I have already got some data where I have implemented a benchmark circuit on the particular area of the FPGA and applied that stresses on the FPGA. Since then, I have taken frequency by ring oscillator to observe the aging condition of the benchmark part and other unused parts. Before giving stress I have taken frequency from all the LUTs of the FPGA. However, the problem what I found that after aging no