Foisal Ahmed

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  1. Dear hamster, Thank you for your reply. It makes my intuition clear. regards, Foisal
  2. Hello, I have a very simple technical question. In Xilinx xc7a35ticpg236-1L Artix-7 FPGA there have only 20800 LUTs found both manual and vivado tools showing also. But in the layout or floor plan, the number of LUTs is more than 20800. Each LUT in the layout plan can be accessed by changing the location through XDC file. But why all LUTs( which is more than 20800) in the layout could not be implemented at a time. Is there any physical constraint? Thanks in advance. Regards, Foisal
  3. Dear jpeyron Thanks for your feedback. I think this might be helpful. Regards Foisal
  4. Can anyone give me the information about the Core voltage of Basys3 Board of the FPGA chipArtix-7, XC7A35T-ICPG236C? How can I change the core voltage to accelerate any operation? Thanks in advance. Regards, Foisal
  5. Dear D@n, Thank you for your nice technical information. Actually, I want to observe some aging effect on the LUTs by giving them some electrical (DC0 or DC1) and high-temperature stress. I have already got some data where I have implemented a benchmark circuit on the particular area of the FPGA and applied that stresses on the FPGA. Since then, I have taken frequency by ring oscillator to observe the aging condition of the benchmark part and other unused parts. Before giving stress I have taken frequency from all the LUTs of the FPGA. However, the problem what I found that after aging not only degraded the used part but also degraded significantly other unused parts where there was no benchmark component during the stress. Actually, my assumption is that the aging mechanism also worked on the other unused part due to the initial value of the LUT 1'b0. You know Inside LUT, there is CMOS circuit and if the initial value is 1'b0 then aging mechanism NBTI is occurring automatically when faced with high temperature. That is the main reason why I want to force all LUTs /register initial value 1'b1 during power-up so that aging effect only occurs in the specific benchmark circuit area. Previously, Xilinx had some direction in this regard using ISE version but I am using Vivado tools. Please see the below Xilinx link: https://www.xilinx.com/support/answers/3123.html https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/destech/html/cd_webpackcontrolling_register_initial_states.html Sorry, I do not know whether my explanation and query are understandable or not. Actually, It will be better for me to know how to give constantly DC Logic 1 stress on to all LUTs of the FPGA. Thanks and regards, Foisal Ahmed
  6. Thanks, BogdanVanca for your reply. The default initial state for all registers, LUT and latches are zero (Logic state 0). Before downloading the specific Verilog file on the FPGA, I want to force the initial value of all LUTs as 1 (logic state ) instead of the default 0 value. So, Where and how I can do this. Please help to solve the Problem. Thanks
  7. I am using Vivado 2015 tools for Basys 3 FPGA Board. I want to fix all of the Register into default Logic state 1. Where and how can I do this? In the Tools or XDC file. Please kindly solve this problem. Thanks for advance. Regards Foisal Ahmed
  8. HI @JColvin, Thanks a lot for this valuable link. In the problem, I have another problem after analyzing that the above problem only shows when I have changed XDC file by manually. To take ring oscillator frequency every time I have to move LUT location changing like BEL, slice etc. Some location does not reset but some location resets automatically. Besides these, In my design have some timing slack which I have not removed yet. Thanks Foisal
  9. HI @jon Is there any tutorial how to use it? Thanks Foisal
  10. Hi@jpeyron Another important thing I found that whenever I forced to change the location of LUT of Ring Oscillator through XDC file, then showing the problem also. Thanks
  11. Hi@jpeyron Yes so my knowledge all jumper set is same and configuration also. Thanks
  12. Hi@jpeyron Thank you for your kind reply. Yes, all six devices are Artix-7 devices basys 3's (3 devices are four month old and 3 devices that not work properly are 1 week old). Not any error in vivado yet. It correctly synthesized and implemented. But whenever I want to download the program in the Artix-7 devices basys 3's they showing the problem which I have mentioned in my post. Thanks
  13. Hi, I am working to establish a Measuring unit for testing FPGA board. I have used Artix-7 Device in the Basys3 FPGA board. My system is automatically measure ring oscillator frequency for the 5s duration of various location. I have used a counter to measure the frequency and showing in the 7-segment display for 5s and reset it after 5s. After 15s next ring oscillator is going to run and showing the same thing. I have successfully implemented and checked for three different Basys3 FPGA board. But the problem is that now it is not working for another three new Artix-7 Devices which I have bought just one month before. Same Verilog program is working in my previous three board but not working for the new three boards. Each operation, I have run 10 ring oscillator sequentially with each for 5s but after running one ring oscillator properly, then another ring oscillator has been gone to zero or sometimes not stop properly at the specific time. I have used the case statement to run individual ring oscillator. Please help me where is my main problem. I think in frequency counter function the clock from ring oscillator showing some problem but why is does not shown in other three FPGA board. The problem shows me very interesting but also painful to fix up it. Thanks