regnon

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  1. Jon 1) I used 192.168.1.11 and 255.255.255.0 on a PC. 2) I was making further trial using same design and example software with an Arty Z7 and the result seems better as the Arty reply to the "ping" command with the IP 192.168.1.10, where my Zybo Z7 remains unreachable when Ping is executed. Does the Arty Z7 and the Zybo Z7 share the same ethernet PHY component? Should I put the Eth0 in the design to the EMIO or to the MIO for the Zybo? Regis
  2. Jon Thanks for your feedback below my answer: 1) I tried with 2 PC, first with windows 10 (result was connection rejected) and second with windows 7 (result was connection timeout) 2) I tried with 2 different internet cable and got same result with the 2 cables 3) for the UART Com, as mentioned if I fix the speed in the bsp, then I have displayed link up then few second after link down, this in a cycle. In case I keep the autodetection of the speed, then the dispay in putty for the UART is as expected and exactly same that in the tutorial... so seems everything looks ok... but when I try to open tera term on a PC to verify ethernet connection then I get connection not authorized on windows 10 and connection timeout on windows 7...which is not what I expect when seeing the tutorial. 4) I did use in the past a preload of petalinux on this zybo z7 and ethernet was working well. BR Regis
  3. Good morning I went through all post related to the use of LWIP ECHO app for ethernet with bare metal OS on Zybo. I also made step by step the tutorial : Getting Started with Zynq Servers for Zybo… but still could not succeed… I'm using Vivado 2018.2 I got the following behaviour: 1) In case I manually setup the speed to 1000 (or to 100) in the bsp as requested in the Getting Started with Zynq Server, the zybo is displaying trhough the UART 'Link up and Link down' alternatively, in the same way the PC connected to the ethernet link is alternatively mentioning the cable as disconnected 2) In case I let the automatic detection of the speed active in the bsp, I do not have anymore the display of link down / link up alternatively and the behaviour looks conform up to the step 11 of the tutorial… but then when trying the step 12, Tera term is not able to connect to the Zybo; mentioning:connexion timeout in one of my PC and Connexion refused in an other PC. I have created static address on a PC. Therefore I'm stuck and would welcome your advise… Best regards Regis Brignon
  4. Hello I face the same issue with a SMT2 JTAG recognized as "Single RS232-HS"... can I get the reprog tool of the Digilent JTAG device Thanks Regis
  5. I'm designing an application using the Audio CODEC of the Zybo Z7. I'm configuring the CODEC by I2C properly and could see data coming from the I2S. Then I realized that each time I programmed the FPGA, the Led 5 of the board was turning ON... even this LED is not at all part of my design!! Never mentioned in my constraints and never mentioned in the verilog wrapper. Then proceeding by elimination when analyzing the constraints, I realized that this LED was turned ON as soon as the I2S clock went enabled... with below constraints: NO LED TURNED ON ##I2S Audio Codec ##set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports BCLK_0]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK ##set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports FCLK_CLK1_0]; #IO_25_34 Sch=AC_MCLK ##set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports RECDAT_0]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports RECLRCLK_0]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC ##Audio Codec/external EEPROM IIC bus set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA But with below constraints enabling the CLOCK... I get the LED turning on in Red, Green or Blue depending... ##I2S Audio Codec set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports BCLK_0]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports FCLK_CLK1_0]; #IO_25_34 Sch=AC_MCLK set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports RECDAT_0]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports RECLRCLK_0]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC ##Audio Codec/external EEPROM IIC bus set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA I'm respecting the pin allocation proposed in the Zybo Z7 manual... therefore I do not understand what is going on... Let me know if someone already faced this situation or have any idea of the phenomena. I"m using Zybo_Audio_Ctrl IP for the I2S below a copy of my design...