Perhaps I am not familiar enough with FPGA design, I am just trying to port this project
to the Arty S7. I already genarate the .mcs image by tweaking the .xdc and scala files, I have to move around things since the Arty board has more clock capable pins on PMOD D connector than Arty S7.
One problem is that after loading .mcs file, the board is not booting correctly, I suspect is because I remove the QSPI clock from scala files, which I did since Arty has a signal QSPI_CLK from L16, but Arty S7 don't have such a connection. My knowledge is limiting me to understand better but I guess the implementation is driving QSPI from that signal instead of CCLK.
Actually I ask about it here
Would you please give me some comments that can point me in the right direction?