mhanuel

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  1. I think I have made some progress, perhaps the issue is too much project dependant but @jpeyron can you check the verilog here and let me know if that make sense please. Appreciated!
  2. Hello @jpeyron Perhaps I am not familiar enough with FPGA design, I am just trying to port this project https://github.com/sifive/freedom to the Arty S7. I already genarate the .mcs image by tweaking the .xdc and scala files, I have to move around things since the Arty board has more clock capable pins on PMOD D connector than Arty S7. One problem is that after loading .mcs file, the board is not booting correctly, I suspect is because I remove the QSPI clock from scala files, which I did since Arty has a signal QSPI_CLK from L16, but Arty S7 don't have such a connection. My knowledge is limiting me to understand better but I guess the implementation is driving QSPI from that signal instead of CCLK. Actually I ask about it here https://github.com/sifive/freedom/issues/52 Would you please give me some comments that can point me in the right direction? Best,
  3. Hello all, Does someone know how can I instantiate the STARTUPE2 primitive in a project that uses only TCL? I am working to port from Arty A7 to Arty S7 and notice the constraint file has missing qspi_sck signal, then the following appears at the Arty S7 .xdc file ## Note: the SCK clock signal can be driven using the STARTUPE2 primitive But the project uses only tcl scripts. How can I workaround this? I found HDLC and Verilog examples under UG953 but I have limited experience on how to use them using TCL. Will appreciate any comments. Best,