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  1. @dgottesm, Normally not needed as you are feeding the input clock to the clock_wizard(MMCM/PLL). You will see in the above pic that IBUF/BUFG are a part of the clock_wizard IP. You just do the port mapping in the RTL and let Vivado synthesis engine do the rest. Yes the above depiction is ok.
  2. @Antonio Fasano, I looked up the Arty Z7-20 and saw that the PS has a 1G Ethernet as hard macro. You should be able to use that. Otherwise in the Pl side, you can also instantiate the Xilinx TEMAC core using the Hardware Evaluation License. You cannot use the above on the Arty Z7-20, your board will not support it, there is no equivalent PHY!
  3. @Aggie Ideally you should be looking at this for your FMC connection. https://github.com/Digilent/digilent-xdc/blob/master/Zedboard-Master.xdc You can copy and paste the above xdc file as your top level xdc file. Then just enable only those FMC pins which you are using in your design (yes of course input clocks, resets, anything else your design is using should also be enabled).
  4. For the benefit of beginners, I have uploaded the work done to GitHub. https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10 Please inform me of anyone sees a problem for the above @ GitHub. Don''t forget to tag me and note that I do not check into this forum everyday.
  5. @Aleksandar, I found this out: https://medium.com/developments-and-implementations-on-zynq-7000-ap/interfacing-a-usb-webcam-and-enable-usb-tethering-on-zynq-7000-ap-soc-running-linux-1ba6d836749d
  6. I know that I am not answering your main Q, but perhaps easier to do... Have your data stored in a BRAM, populate the BRAM contents using a .coe file (or just initiate it in your RTL). Then make your design read this BRAM and generate the pulses.
  7. dpaul

    vivado 2017.4

    What do you mean? Please define "not showing any results" Can you please re-phrase your question for a better understanding of the problem?
  8. @aiswarya, A a normal FIFO is not meant to have an address. A write cmd writes into the FIFO an the read cmd reads out from the FIFO. In the axi fifo all this complexity is handled by the axi logic wrappers that come embedded within the fifo IP. Are you running a sim? You should! In sim, you should be able to see fifo writes when a write axi cmd is issued on the S_AXI side and a read cmd issued on the M_AXI side should empty the FIFO.You should also be able to see where the problem is occurring in your datapath.
  9. Hi @jpeyron, Thanks for posting the link. But I am constraining the tmdi input clock at the top level. I tried again and get the same error message. Note that I had done a similar IP upgrade of the dvi2rgb and rgb2dvi cores as the author of the link mentioned you had done. # < 80MHz TMDS clock #create_clock -period 12.5 [get_ports TMDS_rx_i_clk_p] create_clock -period 13.468 -waveform {0.000 6.734} [get_ports TMDS_rx_i_clk_p] hdmi_vdma.xdc
  10. Hello all, I have got hold of the Digilent Zybo Video Workshop, Paris, France, 23.03.2017 PDF. I am following "Task Two" there in, at page 16 - Create a pass-through video pipeline. I want to implement this using a Z7-10 and using Vivado 2017.4. I will be using 720p resolution video (TMDS input clock < 80MHz). I have build the BD and is as shown below. This you can find in the PDF at page 26 and is exactly the same. The design is synth properly but during bitstream generation I get the following error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The compu
  11. There were 3 changes. 1. HDMI_TX_HPD is input, HDMI_RX_HPD is output. Leave HDMI_TX_HPD unconnected, if not used. 2. I was constraining hdmi_rx_clk_p_i to 80MHz, but then I changed it to 74.25MHz (create_clock -period 13.468 .......). I think even if I constrain it to 80MHz, it would still work! 3. Then I was making a stupid mistake and I think it was the biggest bottleneck. I was making a typo error where I was connecting some signal of std_logic_vector(2 downto 0) to another of std_logic_vector(0 to 2).
  12. @elodg and @ArKay99, Thanks to both of you! The design is now running. I can now get the o/p of my laptop to a Fujitsu monitor at 720p.
  13. @elodg Resurrecting this thread again.... I am now driving hpd_tx and hpd_rx now high. But I still don't get anything on my display. I know that others have done it, have read through their threads, but still can't understand what I am doing wrong. I am constraining the cores to 80MHz for 720p resolution (as I am using -1 speed grade FPGA, ZyboZ7-10). My source, laptop display I have set to 1280x720. The display monitor is Fujitsu which I think should be capable of displaying resolution. For the clock generator I am using a PLL whose i/p is 125MHz and supplies th
  14. dpaul

    HDMI_IN Arty Z7-20 ERROR

    I don't know French and this is an English forum! Are you also using Vivado 2016.4 or some other version? Try to re-generate the IP cores.