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  1. The problem is solved. I used the XGpio_Discrete*() and it worked.
  2. I don't know the communication b/w the Pmod ESP32 and the smartphone. But driving the Pmod from Zybo z720 should be straightforward. You have to implement the SPI master core (you have Xilinx IP cores free to use) on the FPGA side which should be able to read/write to the SPA slave, i.e Pmod ESP32.
  3. You are not specific regarding the type of "implementation " you mean here - Make own implementation in Micorcontroller Part of SoC; Make own implementation in PL Part or FPGA 1. Signal gen can also be done using look-up tables. Depending on the nature of signal to be generated, the "look-up" table method is supposed to be efficient. The savings in processing time can be significant, because retrieving a value from memory (where loop-up table values are stored) is often faster than carrying out an "expensive" computation or input/output operation. 2. That is your homework, search out
  4. Hello, I have a Z7-10 board. I am writing software for the Zynq, which will access 8 GPIO pins via the PL (using the AXI GPIO IP). These will be 4 each on-board LEDs LD0-LD3 (to be configured as output) and DIP switches SW0-SW3(to be configured as input). The BD is shown below. The offset and high address are shown below in the SS. My target is to read the status of the 4x slide switches and write those values back to the LEDs in order. So to achieve that, after initializing the GPIO, I have also set the direction of the bits as shown in the following 2 lines. Status =
  5. @dgottesm, Normally not needed as you are feeding the input clock to the clock_wizard(MMCM/PLL). You will see in the above pic that IBUF/BUFG are a part of the clock_wizard IP. You just do the port mapping in the RTL and let Vivado synthesis engine do the rest. Yes the above depiction is ok.
  6. @Antonio Fasano, I looked up the Arty Z7-20 and saw that the PS has a 1G Ethernet as hard macro. You should be able to use that. Otherwise in the Pl side, you can also instantiate the Xilinx TEMAC core using the Hardware Evaluation License. You cannot use the above on the Arty Z7-20, your board will not support it, there is no equivalent PHY!
  7. @Aggie Ideally you should be looking at this for your FMC connection. https://github.com/Digilent/digilent-xdc/blob/master/Zedboard-Master.xdc You can copy and paste the above xdc file as your top level xdc file. Then just enable only those FMC pins which you are using in your design (yes of course input clocks, resets, anything else your design is using should also be enabled).
  8. For the benefit of beginners, I have uploaded the work done to GitHub. https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10 Please inform me of anyone sees a problem for the above @ GitHub. Don''t forget to tag me and note that I do not check into this forum everyday.
  9. @Aleksandar, I found this out: https://medium.com/developments-and-implementations-on-zynq-7000-ap/interfacing-a-usb-webcam-and-enable-usb-tethering-on-zynq-7000-ap-soc-running-linux-1ba6d836749d
  10. I know that I am not answering your main Q, but perhaps easier to do... Have your data stored in a BRAM, populate the BRAM contents using a .coe file (or just initiate it in your RTL). Then make your design read this BRAM and generate the pulses.
  11. dpaul

    vivado 2017.4

    What do you mean? Please define "not showing any results" Can you please re-phrase your question for a better understanding of the problem?
  12. @aiswarya, A a normal FIFO is not meant to have an address. A write cmd writes into the FIFO an the read cmd reads out from the FIFO. In the axi fifo all this complexity is handled by the axi logic wrappers that come embedded within the fifo IP. Are you running a sim? You should! In sim, you should be able to see fifo writes when a write axi cmd is issued on the S_AXI side and a read cmd issued on the M_AXI side should empty the FIFO.You should also be able to see where the problem is occurring in your datapath.
  13. Hi @jpeyron, Thanks for posting the link. But I am constraining the tmdi input clock at the top level. I tried again and get the same error message. Note that I had done a similar IP upgrade of the dvi2rgb and rgb2dvi cores as the author of the link mentioned you had done. # < 80MHz TMDS clock #create_clock -period 12.5 [get_ports TMDS_rx_i_clk_p] create_clock -period 13.468 -waveform {0.000 6.734} [get_ports TMDS_rx_i_clk_p] hdmi_vdma.xdc
  14. Hello all, I have got hold of the Digilent Zybo Video Workshop, Paris, France, 23.03.2017 PDF. I am following "Task Two" there in, at page 16 - Create a pass-through video pipeline. I want to implement this using a Z7-10 and using Vivado 2017.4. I will be using 720p resolution video (TMDS input clock < 80MHz). I have build the BD and is as shown below. This you can find in the PDF at page 26 and is exactly the same. The design is synth properly but during bitstream generation I get the following error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The compu