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  1. I'm trying to create a system that does some image processing using HDMI in and outputting the result via HDMI out. I tried to connect dvi2rgb directly to rgb2dvi as shown below but when I connect the output to a monitor it tells me the format is not supported even though both IP are setup for 1080p. I brought the lock signal from dvi2rgb out to an led and it is being asserted so I'm not sure what the issue is here. The config of the two IP is shown below, any idea what could be causing this problem?
  2. The example used on the reference page isn't much good to me as loads the data into the DRAM. I want a system that just passes an image through a image processing block and back out again.
  3. Hi Sergiu, The "lock" signal is connected to the lock status of the DVI2RGB block while the "locked" is connected to the lock status of the AXIS to RGB block. Both are connected to LEDS but only the "lock" signal is asserted. I did some more debug and I can see the AXIS to RGB block is underflowing but it is receiving data from the RGB to AXIS block so I'm not sure why it is underflowing. Regards, Cathal
  4. I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it nev
  5. Sorry for the delay, here is a screen shot of the critical warning I get and here is the summary of the timing report Do you know if there a way to dump out the timing report to a log file in Vivado?
  6. Hi Jon, I managed to fix the timing errors by disable "add BUFG to PixelClk" and I can now input video on the HDMI and output it on the VGA. What is this feature used for? It would also be usual if the document for these IP contained a recommended setting for typical use cases, I wasn't ever 100% clear on what should be set in the parameter IP settings. One side affect of using the DVI and VGA IP is that my zynq processing system no longer seems to work correctly. I used to be able to boot Linux on it and since adding these IPs to the PL it fails to boot, any ideas wh
  7. The system shown above was generated with Vivado 2017.2. I have seem the tutorial you provided as well and this was generated with Vivado 2016.4 and I see the same timing issue when generating the bit stream for this. I reviewed the documents you pointed to but they don't say anything about timing issues. They also don't give a clear indication what the parameters of the two IP should be in order to get a certain video format in or out. Is there any simple example available for the zybo where it is just dvi2rgb connected to rgb2vga?
  8. I'm trying create a PL subsystem that takes a HDMI video in and outputs it on the VGA. I got the digilent IP from this github and I created a HDMI in to VGA out loop in Vivado as shown below I have set the clock wizard up to provide 200MHz to the dvi2rgb block and the clock wizard block has an input clock 125MHz. I programmed the dvi2rgb block with the following config After trying to generate the bitstream for this I'm getting critical errors at the implementation stage saying it can't meet timing. It managed to g