tekson

Members
  • Content Count

    18
  • Joined

  • Last visited

About tekson

  • Rank
    Member

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. link:https://drive.google.com/open?id=1m0Foi2VJGceonyG8LFCa4gOeeVCHiELc
  2. Hi, tried it by moving the jumper JP6 to jtag mode. But no signal in the display.
  3. Hai, bitstream generation is successfully completed when i add few lines of code in my previous xdc to the latest one you provided. And i got output on display. but i m not sure whether this is the correct one.
  4. thanks for the reply but now i got error while implementation error. error snapshot attached.
  5. hi, the link for the project attached https://drive.google.com/open?id=1hlaMs-wpVEnfhxweX5hLNWDSwtAgCoI8 As i have only the licencse of vivado 2017.4, so I can't do it in 2018.2. Thanks,
  6. HI, Thanks for the support. Here i m attaching the link of my project folder in vivado 2017.4. https://drive.google.com/open?id=1qYPBff-duWx9FVwLuWtWumjfKbBOETFE
  7. Dear all, I tried to make a block design as per the zybo HDMI demo in vivado 2017.4 version. I m using zybo z7-10 While generating bit stream it is showing error something related to hdmi. here i m attaching the screen shot of error message . Can anyone please help me to figure out the error. Thanks in advance Regards, Mebin
  8. Hi, I tried to run HDMI demo 2016.4 in vivado 2016.4 version. but while implementation process it shows errors. Error screenshot attached. Before implementation it shows some errors like some ips are locked. Can anyone please help me to solve this. Regards, Mebin
  9. The 24 bit RGB , I'm using is the DLP 2000 TI mini projector evaluation board and zync board i m using is the Xilinx Zynq-7000 SoC ZC702 Evaluation Kit
  10. Hi all, i want to interface RGB(24 -bit) display with zynq 7000. How can I do this. I don't have any idea about how to do this. Can anyone help me .
  11. tekson

    Delay

    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  12. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI
  13. Thanks for your quick reply. When I used a monitor with HDMI input, it worked properly and i got linario desktop on the Monitor. The reason for HDMI-VGA converter is not working with VGA monitor is due to device tree issues or any other issues. Can you please specify, why this happens. Do I need to add new device tree files from diligent for zybo z7-10?