GN_ghost

Members
  • Content Count

    2
  • Joined

  • Last visited

About GN_ghost

  • Rank
    Newbie

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. GN_ghost

    Zybo Z7 PMOD IO speed

    Thank you very much for your reply! Well, I understand how to terminate a LVDS pair generally, but it just couldn't be implemented in this board. (adding resistor near the SoC) Beside using the PMOD connector, I found that our camera MIPI connector indeed has proper termination (R49 R50 R51). Since the reference manual mentioned that the routing of D-PHY signals follows xilinx's app note, can I assume that those lines are 50 Ohm lines? If it is 50Ohm lines, do you think it is possible to just remove R46 R47 R48 R54 R55 R56, and change R49 R50 R51 to 100Ohm resistors to convert those lines into LVDS pairs? Thanks again.
  2. GN_ghost

    Zybo Z7 PMOD IO speed

    I have a question about how to connect zybo z7 to a ADC with LVDS input and output running at 200MHz. The zybo z7 need to provide clock to the ADC at 200 MHz and receive data at this speed. The ADC's interface is indeed LVDS yet this zybo z7 board's IO bank are all 3.3V powered, which means that it cannot use the internal termination. I think I have two way to make it work. 1. transmit data and clock in a single-ended way and do the single-ended to differential conversion on my ADC board. 2. transmit data in LVCMOS33 and do level conversion in ADC board. The problems I have are that: 1. Is that ok to transmit a signal in single-ended way at 200MHz? I have no experience on doing that before. 2. If I use LVCMOS33, since I still cannot use the on chip termination, is that enough for me to just terminate transmission lines at the ADC's LVDS driver side? 3. What is the impedance on the FPGA IO pins when it is in LVCMOS mode? Thanks a lot!