Tim S.

I found my answer at:
https://digilent.com/reference/programmable-logic/documents/git
 

Hi to the community,
I have refreshed this design. Now with support for:
Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Xilinx Zynq-7000 SoC There are four designs total. 3 IPI-BD designs plus a C program, one for each of the mentioned development boards. And 1 straight Verilog-HDL design that targets either of the Arty A7 and Arty S7 boards.
The examples are kept at beginner level and are based on textbook and datasheet study, as well as HDL and FPGA work experience.
The Pmod HYGRO is polled and then its readings displayed in human-readable text on the 16x2 LCD.
Read more at:
https://timothystotts.github.io/2023/04/30/refresh-of-the-fpga-iic-hygro-tester.html
Cheers.
Tim S.
 

Over two years ago, I authored a driver for the Pmod SSD that uses minimal CPU overhead. You can find it in the Project Vault. I titled it MuxSSD. Regards, Tim S.
 

Months ago, I wrote a Pmod HYGRO driver in VHDL without block diagram. The Pmod HYGRO's I2C requirements are odd. I'd be glad to mention my findings if you are debugging waveform or message-order issues for reading the HYGRO's measurement registers.

Hi to the community.
I have posted on GitHub a FPGA design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS.
https://timothystotts.github.io/2020/09/12/hygro-sensor-readings-tester-on-arty-a7.html
Regards,
Tim S.

Today I authored a brief post to introduce a simple FPGA design that I shared on GitHub. The design inputs a 24-bit color palette value from a keypad; and then that color value is mixed on a discrete RGB LED as well as text on a small display.
https://timothystotts.github.io/2020/08/31/colors-palette-tester-on-arty-a7.html
Regards,
Tim S.
 

Hi @JColvin,
I'd be glad to have the project(s) shared with the community on Digilent's own Wiki pages.
Note that I'll do my best to keep the Git repository copacetic.
Thanks!
Tim S.

I authored a minimal Vivado IP design to control a single Pmod SSD with extension cable on a single jack of a FPGA board. The IP is called MuxSSD and allows writing either digit at any time with no need to use a fast GPIO trick in the application C code.
This driver is part of my previously mentioned Accelerometer Tester design.
The project is hosted at: https://github.com/timothystotts/fpga-serial-acl-tester-1 .
Tim S.

Hi to the community. I would like to mention that I have posted a FPGA design that memory byte tests the Pmod SF3 with 256Mbit N25Q flash chip.
You can find a link to this project at http://timothystotts.github.io/.
The name of the project is fpga-serial-mem-tester-1 .
The project sources contain some features beyond testing the QSPI flash chip.
Regards,
Tim S.