Tim S.

Two example codes, thus far, as a UIO driver experiment, licensed GPL-2.0, can be found at: https://github.com/timothystotts/Zybo-Z7-OS-1/tree/independent/Tim_S_project_1/project-spec/meta-user/recipes-apps/uio-gpio-test/files

I added functionality to control the Zybo Z7-20 RGB LEDs based on a combination of switch selections, button presses, and Pmod PIR interrupts. Find the example attached. Find my full project at: https://github.com/timothystotts/Zybo-Z7-HW-1 https://github.com/timothystotts/Zybo-Z7-OS-1 branches: independent/Tim_S_project_1 Cheers. Tim S.

I put together a UIO example PetaLinux program that waits for GPIO interrupts from 2 Pmod PIR, Buttons, and Switches, and outputs to the four basic LEDs. This experiment answered my UIO questions for these components. References listed at the head of the file.

I answered my own question on testing the Pmod HYGRO from the command-line. Retrieving the raw values: root@Petalinux-2022:~# i2ctransfer -y 3 w1@0x40 0x00 root@Petalinux-2022:~# i2ctransfer -y 3 r4@0x40 0x5f 0xcc 0xa4 0x68 root@Petalinux-2022:~# i2ctransfer -y 3 w1@0x40 0x00 && usleep 100000 && i2ctransfer -y 3 r4@0x40 0x5f 0xdc 0xa3 0xe8 root@Petalinux-2022:~# i2ctransfer -y 3 w1@0x40 0x00 && usleep 100000 && i2ctransfer -y 3 r4@0x40 0x5f 0xe0 0xa3 0xe8 Processing the raw values to Fahrenheit and RH% with a Python shell on the workstation: >>> ((225 * 0x5fe0) / (2**9) - 4000) / 100 67.859375 >>> ((225 * 0x5fdc) / (2**9) - 4000) / 100 67.841796875 >>> ((225 * 0x5fe0) / (2**9) - 4000) / 100 67.859375 >>> ((0xa468 * 625) / (2**12)) / 100 64.22119140625 >>> ((0xa3e8 * 625) / (2**12)) / 100 64.02587890625 So the sensor reads my desk space as 67.86 degrees Fahrenheit and 64% Relative Humidity. I also found an old, probably incomplete, GPLv3 I2C kernel driver for PmodTMP2, which is similar in concept. https://github.com/inipro/zynqmp_linux/blob/master/petalinux/workspaces/pmodtmp2/pmodtmp2.c

Hi. I'd like to ask if Digilent staff or forum users have any tips for finding PetaLinux or Embedded Linux documentation on any of the following: 1. xlnx,axi-gpio - how to read on edge or level interrupt from Zynq PL pins by adding to the device tree and not using the sysfs gpio-demo. Polling is not sufficient. Purpose: connect Pmod PIR. 2. xlnx,axi-iic - how to configure the device tree for AMBA PL Xilinx IIC, and perform more custom commands than i2cset and i2cget allow. I am thinking a custom kernel driver is in order. Purpose: read Pmod HYGRO readings. 3. xlnx,axi-quad-spi - how to configure the device tree for Mode 0 or Mode 3 standard devices for AMBA PL Xilinx Quad SPI in standard SPI mode. I am thinking a custom kernel driver is in order. Purpose: read the Pmod ALS reading, read the Pmod ACL2 readings. 4. xlnx,axi-quad-spi - how to configure the device tree AMBA PL Xilinx Quad SPI in Quad SPI mode, to connect a NOR flash to the Zynq PL and have it show up as a MTD device. The Digilent Demo already shows how to add the NOR flash as MTD device for the Zynq PS. Purpose: MTD block device access of the Pmod SF3. Just a note that this is a hobby project, not school or employment, and that I do have professional background in Embedded Linux. Thanks for any input. Cheers. Tim S.

I found my answer at: https://digilent.com/reference/programmable-logic/documents/git

https://digilent.com/reference/programmable-logic/zybo-z7/demos/petalinux I would like to work with the 2022.1 version of the Zybo Z7-20 PetaLinux demo. There is a link for the PetaLinux BSP. But where is the GitHub repository for the Vivado project that generates the hardware platform? I know that that is not required for executing the demo, but I may wish to customize the Zynq PL. Thanks, Tim S.

Hi to the community, I have refreshed this design. Now with support for: Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Xilinx Zynq-7000 SoC There are four designs total. 3 IPI-BD designs plus a C program, one for each of the mentioned development boards. And 1 straight Verilog-HDL design that targets either of the Arty A7 and Arty S7 boards. The examples are kept at beginner level and are based on textbook and datasheet study, as well as HDL and FPGA work experience. The Pmod HYGRO is polled and then its readings displayed in human-readable text on the 16x2 LCD. Read more at: https://timothystotts.github.io/2023/04/30/refresh-of-the-fpga-iic-hygro-tester.html Cheers. Tim S.

@engrpetero, that's an excellent question: Is the Vitis folder structure documented? Honestly, I would assume it is, in one of Xilinx's Vitis or methodology documents; but I actually don't know. (I worked with software and FPGA hardware, separate ICs of separate manufacturers, long enough that I found it intuitive enough to keep going. Vitis is based on Eclipse, which is the same basic tool flow for may tools now.) I learned SDK from the Digilent tutorials, and before they provided Vitis tutorials, I jumped in and found my way around by reading all information provided by the Vitis tool's Dialogs, as well as intuition from using other Eclipse-based tools. I hope you find that documentation to help you along. Cheers, Tim S.

@engrpetero, I used Vivado and Vitis on Ubuntu, mostly. I noticed that xil_printf.h just references an extern. To assist you: $ find /opt/Xilinx/Vitis/2021.2 -name '*.[hc]' -exec grep -i -l 'XUartLite_CfgInitialize' '{}' ';' /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_6/src/xuartlite_sinit.c /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_6/src/xuartlite.c /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_6/src/xuartlite.h /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_4/src/xuartlite_sinit.c /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_4/src/xuartlite.c /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_4/src/xuartlite.h /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_5/src/xuartlite_sinit.c /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_5/src/xuartlite.c /opt/Xilinx/Vitis/2021.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_5/src/xuartlite.h There should be a "xuartlite.h" in your BSP. [EDIT.] Your platform might have headers located in more than one location under the folder structure. Try using File Explorer to search for xuartlite* .

@engrpetero, the following is the main() routine of a MicroBlaze with UART Lite that I put together in the past. https://github.com/timothystotts/fpga-serial-acl-tester-3/blob/main/ACL-Tester-Design-MB/Vitis-Sources/ACL-Tester-Design-App/freertos_acl2_main.c It appears that I did not include a UART Lite header, but only "xil_printf.h". I recommend tracing the contents of your platform's xil_printf.h to a UART call; but you'll need to expect that for your platform, the #define parts of xil_printf will use the Zynq PS and not a Zynq PL peripheral, and that the sources may be entirely different. You could also try GIT cloning that full example: https://github.com/timothystotts/fpga-serial-acl-tester-3 and generate the Arty A7-100 MicroBlaze example, and trace the xil_printf to MicroBlaze sources, which may be the same as for your UART Lite added to Zynq PL. Such an approach would be recommended if you can't find an online example; and I'm not sure what to suggest beyond that.

@engrpetero, you may need to Reset Sources for both of those Board Support Package definitions show in your screenshot. Note that the FSBL isn't your bare metal project; it's Xilinx's own First Stage BootLoader that loads your Zynq PL (FPGA) bitstream and Zynq PS (processor) ARM program from flash memory. The standalone definition is your bare metal program's Xilinx/3rd-party BSP sources exported from the IP blocks in Vivado. Also, you will to create an Application project with configuration that points to the standalone platform as the platform it is using. That Application Project is where your bare metal + standalone main() would go. If that isn't enough for the right header file appearing, others on the forum may also have ideas...

@engrpetero, after running Generate Bitstream, did you Export your Design as a Fixed Platform from Vivado to create an .XSA file, and then import that file with Update Hardware Specification (right-click on the Vitis platform project)? Also, after you update the platform in Vitis, you may need to Regenerate BSP Headers/Sources by opening the BSP project file (located under the platform's hierarchy in Vitis' workarea) and clicking that button.

Hi @zygot, I've had great success running Vivado/Vitis hobbies on Ubuntu 22.10 on a https://hpdevone.com/. I understand that, officially, I should be using Ubuntu 22.04 instead. Your millage may vary. Tim S.

Over two years ago, I authored a driver for the Pmod SSD that uses minimal CPU overhead. You can find it in the Project Vault. I titled it MuxSSD. Regards, Tim S.

Now with support for: Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Xilinx Zynq-7000 SoC. Note that this project is kept as a intermediate-level design that students, hobbyists, and FPGA enthusiasts may find interesting. The previous FPGA Serial Memory Tester projects were combined into one project using Vivado/Vitis 2021.2. You can find it at: https://github.com/timothystotts/fpga-serial-mem-tester-3 Note that for the two Arty boards, three examples are available: IPI-BD MicroBlaze, VHDL RTL, and SystemVerilog RTL.

Now with support for: Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Xilinx Zynq-7000 SoC. Note that this project is kept as a intermediate-level design that students, hobbyists, and FPGA enthusiasts may find interesting. The previous FPGA Serial Memory Tester projects were combined into one project using Vivado/Vitis 2021.2. You can find it at: https://github.com/timothystotts/fpga-serial-mem-tester-3 Note that for the two Arty boards, three examples are available: IPI-BD MicroBlaze, VHDL RTL, and SystemVerilog RTL.

Dr. Saha, Thank you for joining the Digilent community. Please also look at AVNET and Xilinx forums for ideas. With a Google search, AVNET has a PDF describing a lwIP demo for Arty A7-35; but I do not know if the software demo is still available for download. Tim S.

The FPGA Colors Palette Tester was updated with a refresh. The project is tested with Vivado/Vitis 2021.2. Three development boards are tested: - Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA - Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA - Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Xilinx Zynq-7000 SoC. https://timothystotts.github.io/2022/07/18/refresh-of-the-colors-palette-tester.html Regards, Tim S.

A refresh of the Accelerometer Tested design can be found at: https://github.com/timothystotts/fpga-serial-acl-tester-3/ The design now supports the following development boards: - Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA - Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA - Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Zyng-7000 SoC. The design includes equivalent examples in Block Design, Verilog-only, SystemVerilog-only, and VHDL-only. The VHDL example includes a minimal OS-VVM test-bench example that can be adapted to run with GHDL on Linux. Tim S.

A MicroBlaze example for the Arty S7-25 has been added to the project. Support for Arty S7-25 is now as complete as support for the Arty A7-100. EDIT: A blog post on the updated project can be found at: https://timothystotts.github.io/2022/06/12/fpga-accelerometer-tester-on-the-arty-s7-25.html

@Model92, you can find a small project I wrote for the Pmod HYGRO at: https://github.com/timothystotts/fpga-iic-hygro-tester-1 I do apologize. The driver is in Verilog-2001, not in VHDL. I have authored some of my examples in one, two, or three languages. I haven't authored all of the examples in all three languages (Verilog, SystemVerilog, VHDL). It should still be useful.

Hi, I purchased an Arty-S7-25. I have three small HDL-only examples that I created, where I ported an Arty-A7-100 design to Arty-S7-25. https://github.com/timothystotts/fpga-serial-acl-tester-3 Now I am looking to make a Microblaze AXI design equivalent, as I did for the other board. Can someone at Digilent point me to where I should look for creating a MicroBlaze AXI + DDR3 design for the Arty S7-20? Specifically, I am not familiar with using both the System Clock and the DDR clock for the DDR3L MIG. Are Digilent customers expected to read through the Xilinx documentation on MIG, DDR3, etc, to understand the nuances of using two external clocks for the MIG? Or has Digilent posted an example that uses the Clocking Wizard and MIG with the two separate clocks? Thanks. Tim S.

At this time, support for the Arty-S7-25 has been added to three of the four Arty-A7-100 projects. - all SystemVerilog RTL - all Verilog RTL - all VHDL RTL

Hi there. Last year I posted on GitHub two projects that implement communication with the Pmod ACL2, targeting the Arty-A7-100 and Zynq-Z7-20 respectively. The past two months I've updated these projects to the Xilinx Vivado 2021.2 with TCL scripts version controlled for recreation of the project and block diagrams. You can find the design refresh at: https://timothystotts.github.io/2021/11/26/refresh-of-the-fpga-accelerometer-tester.html and https://github.com/timothystotts/fpga-serial-acl-tester-3/ Note that there are five example Xilinx Vivado/Vitis projects that implement the same function: - all SystemVerilog RTL - all Verilog RTL - all VHDL RTL - Xilinx MicroBlaze system - Xilinx Zynq-7000 system Regards, Tim S.