Tim S.

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Tim S. last won the day on July 23

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  1. @JColvin, Thanks. Regards, Tim S.
  2. Hi to the community again. I converted my Accelerometer Tester project to execute on a Zybo-Z7-20. You can find more information by looking for project fpga-serial-acl-tester-2 at my homepage: http://timothystotts.github.io/ Regards, Tim S.
  3. Hi @JColvin, I'd be glad to have the project(s) shared with the community on Digilent's own Wiki pages. Note that I'll do my best to keep the Git repository copacetic. Thanks! Tim S.
  4. Hi. I'd liike to report a few bugs I discovered in the vivado-library IP. The bug fixes are committed to https://github.com/timothystotts/vivado-library in the branches. git log remotes/origin/zybo-z7-20-vivado-2020.1 --name-only For PWM_2.0 , the System Verilog code source file ip/PWM_2.0/hdl/PWM_AXI.sv mixed a blocking and non-blocking assignment in a combinatorial process. My understanding is that all assignments in a combinatorial block should be blocking assignment so that Xilinx Vivado does not infer latches. It was also necessary to update the Makefile to be compatible with Vivado 2020.1 . Additionally, the C source file ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/intc.h included a Xilinx C header with camel case name instead of lowercase. This error does not show on Windows 10, but does show on Linux where the file system is case-sensitive. Finally, Pmod SF3 and Pmod CLS required updating their XSPI driver to not overwrite in the GNU AR contents with an outdated XSPI driver. I would recommend updating Pmod SF3 to use a configuration of the Xilinx AXI QSPI IP that is configured for a 256 Beat FIFO instead of a 16 Beat FIFO, and to specify that the memory type is Micron. Regards, Tim S. commit 238b8ed08331473a288c0ca3522ca0b6a5e4423a Author: Timothy Stotts <[email protected]> Date: Thu Jul 30 14:07:27 2020 -0400 The PmodCLS_v1_0 was repackaged under Linux as the Group File Wizard indicated required merging. ip/Pmods/PmodCLS_v1_0/component.xml commit a435c1ba6294fdff7742bcf465c27fda11ac962b Author: Timothy Stotts <[email protected]> Date: Thu Jul 30 14:05:07 2020 -0400 The include xscugic.h must be specified in all lowercase to successfully compile on case-sensitive file systems, such as Linux EXT4. This was corrected in intc.h of IP PmodSF3_v1_0 ip/Pmods/PmodSF3_v1_0/component.xml ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/intc.h commit 52b2d6f3801f5601f6a8fc7ad709d2041dc3f557 Author: Timothy Stotts <[email protected]> Date: Thu Jul 30 14:02:53 2020 -0400 The SystemVerilog source for PWM_2.0 contained a mix of blocking and non-blocking assignment, resulting in an inferred latch. This was corrected. The PWM_2.0 was repackaged with the updated source file PWM_AXI.sv . ip/PWM_2.0/component.xml ip/PWM_2.0/hdl/PWM_AXI.sv commit a7d5c144faa4e64b3a8667bfe278733643b55502 Author: Timothy Stotts <[email protected]> Date: Wed Jul 29 23:28:23 2020 -0400 The PWM 2.0, PmodCLS, PmodSF3 drivers were updated for usage on the Zybo Z7-20 with Vivado 2020.1 . ip/PWM_2.0/component.xml ip/PWM_2.0/drivers/PWM_v1_0/src/Makefile ip/Pmods/PmodCLS_v1_0/component.xml ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi.c ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi.h ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_i.h ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_l.h ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_options.c ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_selftest.c ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_stats.c ip/Pmods/PmodCLS_v1_0/src/PmodCLS_axi_quad_spi_0_0/PmodCLS_axi_quad_spi_0_0.xci ip/Pmods/PmodCLS_v1_0/src/PmodCLS_axi_quad_spi_0_0/PmodCLS_axi_quad_spi_0_0.xml ip/Pmods/PmodCLS_v1_0/src/PmodCLS_pmod_bridge_0_0/PmodCLS_pmod_bridge_0_0.xci ip/Pmods/PmodCLS_v1_0/src/PmodCLS_pmod_bridge_0_0/PmodCLS_pmod_bridge_0_0.xml ip/Pmods/PmodSF3_v1_0/component.xml ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/PmodSF3.c ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/PmodSF3.h ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/intc.c ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi.c ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi.h ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_i.h ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_l.h ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_options.c ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_selftest.c ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_stats.c ip/Pmods/PmodSF3_v1_0/src/PmodSF3_axi_quad_spi_0_0/PmodSF3_axi_quad_spi_0_0.xci ip/Pmods/PmodSF3_v1_0/src/PmodSF3_axi_quad_spi_0_0/PmodSF3_axi_quad_spi_0_0.xml ip/Pmods/PmodSF3_v1_0/src/PmodSF3_pmod_bridge_0_0/PmodSF3_pmod_bridge_0_0.xci ip/Pmods/PmodSF3_v1_0/src/PmodSF3_pmod_bridge_0_0/PmodSF3_pmod_bridge_0_0.xml commit 73d14c6899228595e853cfa50ad6f2817ffb34a4 Merge: a33ba97 8b2d675 Author: Timothy Stotts <[email protected]> Date: Wed Jul 29 15:54:44 2020 -0400 Merge remote-tracking branch 'remotes/origin/feature/pmod_update' into zybo-z7-20-vivado-2020.1
  5. Hello again to the community. I converted my Arty-A7-100 project of a SPI Memory Tester to execute on a Zybo-Z7-20. The design is in Xilinx Vivado and Vitis 2020.1 . You can find a link to the project on my GitHub home page. https://timothystotts.github.io/#fpga-serial-mem-tester-2 Regards, Tim S.
  6. If all of this still fails, you can try rebooting the computer and plugging into a different USB port on the PC; and powering the Zybo Z7 from a wall jack power supply instead of the USB port. Beyond that, I have no more advice. Best of luck! Tim S.
  7. @MichaelZ, A few more tips on TeraTerm on Windows 10. Check that the COM port used by the Zybo Z7 is without warnings and that you are using the correct COM number, such as COM1, COM4, etc. Then configure your TeraTerm session to select the correct COM Port with the settings set in the ZYNQ7 Processing System IP. While the connection is Live, you may need to reset the terminal so that the behavior instructed by those non-printable characters is reset and you start with a fresh terminal. Reset the terminal: Clear the buffer: If you find that the new settings work, you can save them as defaults when TeraTerm first runs. Regards, Tim S.
  8. Hi @MichaelZ, I have a Zybo Z7 design I made from last year. I assume it is in working condition still. What I'd like to show you is where you can double-check the baud rate of the PS UART1 that connects to the USB port. In the Vivado block design, check for Interface Ports connectivity on the ZYNQ7 Processing System: In the Vivado block design, Customize Block... for the ZYNQ7 Processing System: Examine the UART1 Baud Rate in the General PS-PL panel: In the ZYNQ7 Processing System's MIO panel, check which pins the UART1 is connected to: Again, this is from a working example with Vivado / SDK 2019.1 . But I have not checked its working state since 2019. Regards, Tim S.
  9. @MIchaelZ, I own an Arty A7 and a Zybo Z7. It's been awhile since I pulled out the Zybo Z7; but I'll mention a few tips. Every UART configuration has a baud rate. I don't know what the defaults are; but you should consider picking a baud rate and double-checking that your IPI-BD system is configured for that baud rate prior to synthesis. Note that the UART function may allow you to select a baud rate higher than 115200; but 115200 is the typical maximum baud rate for UART functionality as it is the common maximum baud rate for modem speeds dating back in history. Whenever I create a design, I always check the baud rate is configured to 115200 baud before synthesizing and downloading. If you connect to a terminal with a different baud rate than what the embedded system is using, you will see either no characters displayed or unreadable text displayed on your terminal session. Additionally, the Arty A7 has an usual behavior when connecting a terminal to the UART. If I use the Linux program screen to connect to the USB-UART tty, the Arty A7 may perform a soft reset (without deconfiguring the implementation bitstream) and start again at the beginning of execution. This soft reset does deconfigure the Microblaze soft CPU; but does not deconfigure (only soft reset) a plain RTL design. Either way; I mention this as the solution is to attach your USB to the Linux box and then connect the terminal before programming the bitstream via the USB JTAG. In that way, the terminal does not interfere with the FPGA configuration state. There may not be a solution for a booting from a bitstream that is programmed to the SPI Program Flash and then connecting the terminal. Another thought is that TeraTerm on Windows might not cause this incorrect behavior. Thanks, Tim S.
  10. Hi to the community. As with the SPI Accelerometer project, I created a top-level architecture diagram of this project, the Serial Flash Memory Tester. It could help a person decide if there are reusable modules for their own project. Regards, Tim S.
  11. Hi to the community. I would like to mention that I have posted a FPGA design that memory byte tests the Pmod SF3 with 256Mbit N25Q flash chip. You can find a link to this project at http://timothystotts.github.io/. The name of the project is fpga-serial-mem-tester-1 . The project sources contain some features beyond testing the QSPI flash chip. Regards, Tim S.
  12. I authored a minimal Vivado IP design to control a single Pmod SSD with extension cable on a single jack of a FPGA board. The IP is called MuxSSD and allows writing either digit at any time with no need to use a fast GPIO trick in the application C code. This driver is part of my previously mentioned Accelerometer Tester design. The project is hosted at: https://github.com/timothystotts/fpga-serial-acl-tester-1 . Tim S.
  13. Some further updates were made to the VHDL sources to include usage of a Pmod SSD at Pmod Jack A. These updates are committed at branch feature/ssd_with_presets. Additionally, the FSM diagrams of the aforementioned architecture sketch are now comprehensive in the Documents folder.
  14. Months ago, I wrote a Pmod HYGRO driver in VHDL without block diagram. The Pmod HYGRO's I2C requirements are odd. I'd be glad to mention my findings if you are debugging waveform or message-order issues for reading the HYGRO's measurement registers.
  15. Some updates were made to the fpga-serial-acl-tester-1 project. The HDL architecture was updated to better software practices.