Tim S.

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  1. Hi to the community. I have posted on GitHub an APSoC design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS. https://timothystotts.github.io/2020/09/14/hygro-sensor-readings-tester-on-zybo-z7.html Regards, Tim S.
  2. Hi to the community. I have posted on GitHub a FPGA design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS. https://timothystotts.github.io/2020/09/12/hygro-sensor-readings-tester-on-arty-a7.html Regards, Tim S.
  3. Today I authored a brief post to introduce a simple FPGA design that I shared on GitHub. The design inputs a 24-bit color palette value from a keypad; and then that color value is mixed on a discrete RGB LED as well as text on a small display. https://timothystotts.github.io/2020/08/31/colors-palette-tester-on-arty-a7.html Regards, Tim S.
  4. @JonK, I still recommend checking the file system for errors. I have seen NTFS file systems require a check and repair after adding and removing thousands of tiny files. Regards, Tim S.
  5. I apologize for skimming the later 90% of this thread. Answering your original question; Windows can sometimes corrupt its filesystem. Consider running a full file system check and repair. Reboot. Regards, Tim S.
  6. Hi to the community. The GitHub repository now has a section for Lab Verification of the Pmod busses. SPI values are captured with Waveforms as digital logic analyzer to a Pmod TPH2. I authored a Python script that will translate Pmod CLS SPI bus activity and Pmod SF3 SPI bus activity (in separate files) into human-readable statements of the bus transfers. The script: https://github.com/timothystotts/fpga-serial-mem-tester-1/blob/master/Lab-Verification/display_pmod_parse_from_spi_spy.py Example data inputs and outputs: https://github.com/timothystotts/fpga-serial-mem-teste
  7. @JColvin, Thanks. Regards, Tim S.
  8. Hi to the community again. I converted my Accelerometer Tester project to execute on a Zybo-Z7-20. You can find more information by looking for project fpga-serial-acl-tester-2 at my homepage: http://timothystotts.github.io/ Regards, Tim S.
  9. Hi @JColvin, I'd be glad to have the project(s) shared with the community on Digilent's own Wiki pages. Note that I'll do my best to keep the Git repository copacetic. Thanks! Tim S.
  10. Hi. I'd liike to report a few bugs I discovered in the vivado-library IP. The bug fixes are committed to https://github.com/timothystotts/vivado-library in the branches. git log remotes/origin/zybo-z7-20-vivado-2020.1 --name-only For PWM_2.0 , the System Verilog code source file ip/PWM_2.0/hdl/PWM_AXI.sv mixed a blocking and non-blocking assignment in a combinatorial process. My understanding is that all assignments in a combinatorial block should be blocking assignment so that Xilinx Vivado does not infer latches. It was also necessary to update the Makefile to be compatible wi
  11. Hello again to the community. I converted my Arty-A7-100 project of a SPI Memory Tester to execute on a Zybo-Z7-20. The design is in Xilinx Vivado and Vitis 2020.1 . You can find a link to the project on my GitHub home page. https://timothystotts.github.io/#fpga-serial-mem-tester-2 Regards, Tim S.
  12. If all of this still fails, you can try rebooting the computer and plugging into a different USB port on the PC; and powering the Zybo Z7 from a wall jack power supply instead of the USB port. Beyond that, I have no more advice. Best of luck! Tim S.
  13. @MichaelZ, A few more tips on TeraTerm on Windows 10. Check that the COM port used by the Zybo Z7 is without warnings and that you are using the correct COM number, such as COM1, COM4, etc. Then configure your TeraTerm session to select the correct COM Port with the settings set in the ZYNQ7 Processing System IP. While the connection is Live, you may need to reset the terminal so that the behavior instructed by those non-printable characters is reset and you start with a fresh terminal. Reset the terminal: Clear the buffer: If you fi
  14. Hi @MichaelZ, I have a Zybo Z7 design I made from last year. I assume it is in working condition still. What I'd like to show you is where you can double-check the baud rate of the PS UART1 that connects to the USB port. In the Vivado block design, check for Interface Ports connectivity on the ZYNQ7 Processing System: In the Vivado block design, Customize Block... for the ZYNQ7 Processing System: Examine the UART1 Baud Rate in the General PS-PL panel: In the ZYNQ7 Processing System's MIO panel, check which pins the UART1 is connected to:
  15. @MIchaelZ, I own an Arty A7 and a Zybo Z7. It's been awhile since I pulled out the Zybo Z7; but I'll mention a few tips. Every UART configuration has a baud rate. I don't know what the defaults are; but you should consider picking a baud rate and double-checking that your IPI-BD system is configured for that baud rate prior to synthesis. Note that the UART function may allow you to select a baud rate higher than 115200; but 115200 is the typical maximum baud rate for UART functionality as it is the common maximum baud rate for modem speeds dating back in history. Whenever I create a