Tim S.

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  1. Hi @jpeyron, Regarding your question on the KYPD: with the clock wizard set as discussed, the MIG UI clock is 86 MHz. If I use the KYPD driver as-is, the GPIO will poll at a frequency based on the CPU clock of the Microblaze. This caused some keys to not be read, or to be read as multiple keys pressed. Only about 1/2 of the keys would detect properly. To solve this, I added a micro sleep call to allow the GPIO of the KYPD columns to settle before polling the rows. With this modification, all of the keys detect correctly using the demo code. u16 KYPD_getKeyStates(PmodKYPD *InstancePtr) { u32 rows, cols; u16 keystate; u16 shift[4] = {0, 0, 0, 0}; // Test each column combination, this will help to detect when multiple keys // in the same row are pressed. for (cols = 0; cols < 16; cols++) { KYPD_setCols(InstancePtr, cols); usleep(5); rows = KYPD_getRows(InstancePtr); // Group bits from each individual row shift[0] = (shift[0] << 1) | (rows & 0x1); shift[1] = (shift[1] << 1) | (rows & 0x2) >> 1; shift[2] = (shift[2] << 1) | (rows & 0x4) >> 2; shift[3] = (shift[3] << 1) | (rows & 0x8) >> 3; } // Translate shift patterns for each row into button presses. keystate = 0; keystate |= KYPD_lookupShiftPattern(shift[0]); keystate |= KYPD_lookupShiftPattern(shift[1]) << 4; keystate |= KYPD_lookupShiftPattern(shift[2]) << 8; keystate |= KYPD_lookupShiftPattern(shift[3]) << 12; return keystate; } Thanks, Tim
  2. Just to make sure my explanation is thorough. The above has a typo. It should read: Linux has a case-sensitive file system whereas Windows has a case-insensitive file system.
  3. Hi @jpeyron, The following solved the missing xspi. 1. Rename pmodOLEDrgb to PmodOLEDrgb under Vivado-library . 2. Add the PmodOLEDrgb IP to the block design. 3. Open the IP in IP Packager. 4. Under File Groups, rename the path driver/pmodOLEDrgb for the xspi to have capital 'P' for Pmod instead of lowercase, for each file. 4. Retarget the IP submodules to Arty A7 100. 5. Regenerate the IP module in the IP packager editor. 6. Close the subproject that opened for PmodOLEDrgb. 7. Remove the IP from the block design. 8. Delete the hardware description from project and file system in the SDK. 9 Re-add the PmodOLEDrgb to the block design, and then Regenerate top design bitstream. 10 Export hardware with bitstream to SDK. 11. Open in SDK from Vivado menu. Best, Tim
  4. Hi @jpeyron, I have a successful design with KYPD and OLEDrgb. The only bug is the ABCD column of the keypad indicates multiple key press and the correct key, at the same time. Thank you for your assistance. Best regards, Tim
  5. Hi @jpeyron, I discovered why the xspi sources are missing. Linux has a case-sensitive file system whereas Windows has a case-sensitive file system. The packaging of the PmodOLEDrgb has mixed folder name alphabet-case of the first character 'p' in the folders PmodOLEDrgb. This causes silent errors on Linux whereas I presume there would be no error on Windows. Best, Tim
  6. Hi @jpeyron, I previously copied the Vivado board files under 2019.1/data/boards/board_files for both the /opt/Xilinx/Vivado/ and /opt/Xilinx/SDK/ directories on Linux. I have had problems with the Vivado_Init.tcl approach where Vivado was inconsistent in finding the additional boards. See this Digilent tutorial. I modified the mig,prj to use the correct 100T (as opposed to 35T) part. Also, the PMOD IP from vivado-library was originally targeted to the classic Arty board. To solve this, I opened the two PMOD in IP Packager and retargeted the IP submodules to Arty A7 100. I noticed that the OLEDRGB PMOD contained the xspi sources in the IP packaging. The system.hdf says as shown in the screenshot. It has the FPGA part selected without the board, as you noticed. With the OLEDrgb removed from the project and only kypd preset, the Microblaze project does execute over JTAG as expected. After adding OLEDrgb, the xspi sources are missing, so the project cannot compile. What option did you select to export the Vivado hardware to the SDK? I use File | Export | Hardware , and I include the bitstream. I select Local to Project. My clocking wizard configuration is the same as your screenshots. Tim
  7. Hi @jpeyron, I switched to the Arty A7-100T. I have imported the latest master git branch of the Digilent vivado-library for use in Vivado 2019.1 . The same missing files compilation error exists. See a screenshot below. Regards, Tim
  8. I am trying to design a PL block design and SDK application to exercise the Pmod KYPD and Pmod OLEDrgb together with Vivado 2019.1 . I downloaded the Vivado-library git release for Vivado 2019.1 . In the SDK, I notice that driver PmodOLEDrgb.h is missing source files xspi.h and xspi_l.h . Where do these sources come from? Tim S.
  9. Hi @jpeyron, The base-linux project provides a complex and highly configurable IP Core for the MIPI RX as part of the Board Design. The core is not included under repo/ of the design. It cannot be customized without a license. And it cannot be synthesized without a license. The name of the MIPI RX also differs from the simpler model of the PCam 5 demo. The demo provides MIPI_CSI_2_RX_0 which is an instance of "MIPI CSI-2 Receiver v1.1". The linux base utilizes an absent mipi_csi2_rx_subsystem_0 which is an instance of "MIPI CSI-2 Rx Subsystem v1.0" containing unlicensed core "MIPI CSI-2 Rx Controller v3.0" (Product Guide 232?). Regards, Tim
  10. Specifically, I am using the WebPACK without the SDSoC voucher.
  11. Hi @jpeyron, I am also using Vivado 2017.4 with SDK and support for Zynq-7000 family only. Tim
  12. The exact error message is "Unlicensed Upgrade IP. Check IP license". The needs purchase link indicates minimum version of Vivado as 2017.10 .
  13. Hi @jpeyron, I am unable to upgrade the IP core. Vivado indicates a need to purchase the IP core. Is this IP core not free with WebPACK? Would the SDSoC license voucher provide access to this core? Best regards, Tim
  14. I downloaded Zybo Z7-20 base linux project from git and ran the create_project.tcl script. On the system.bd, there are IP that require a license and are not gratis license. Specifically, the /mipi_csi2_rx_subsystem_0 requires an IP Core license for its sub-component bd_0ac3_rx_0 which.is MIPI CSI-2 Rx Controller. How can I proceed from here for generating a working Zybo Z7-20 linux demo? Thanks. Tim
  15. Tim S.

    Zybo Z7-20 audio interrupt

    Hi @jpeyron, I have examined some of the d_axi_i2s_audio Digilent IP Core sources. It appears that the control of the fifo_4 and fifo_32 fifo instances might be dependent on the AXI4 Stream and AXI4 Lite all running on the same clock. I had attempted to run the AXI4 Lite at 50 MHz and the AXI4 Stream run at a matching-phase 100 MHz. Best I can tell from the STATUS register is that the FIFOs fill with data and then are not dequeued. If I utilize a second M_GP (M_GP1) on the Zynq 7 Processing System and execute it at 100 MHz instead of 50 MHz; and interconnect the Audio DMA cores all at the same 100 MHz; then the audio I2S functions according to the Audio DMA example. Best regards, Tim