Tim S.

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  1. @jge64: I have built the pcam example with Vivado 2016.4 and Vivado 2018.2 . With 2016.4 I observed an error with processing with RGB color space turned on. With 2018.2 I observed a refresh rate error at 15 fps. I do not know if @jpeyron is accurate that the timing closure error is benign.
  2. Hi @jpeyron, I followed the Digilent on-line documentation for the project and the demo is working on my board. Thank you for confirming in advance that the timing issue on the "special" IO Delay Buffer instances can be ignored. I will go ahead and read the relevant Xilinx App Note on the special IO Delay Buffer configuration for my own edification. Best, Tim
  3. The current ZIP-file release of the Zybo Z7-20 pcam-5c demo does not achieve timing closure with Xilinx Vivado 2016.4 . The constraint from ZyboZ7_A.xdc: create_clock -period 2.976 -name dphy_hs_clock_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p] does not achieve timing closure for two signal paths in system_i/MIPI_D_PHY_RX_0, both related to DDLY A B Name Path 62 Slack -3.303ns Source dphy_data_hs_n[0] (input port clocked by dphy_hs_clock_p {rise@0.000ns fall@1.488ns period=2.976ns}) Destination system_i/MIPI_D_PHY_RX_0/U0/DataLaneGen[0].DPHY_LaneSFEN_X/HSDeserializerX/Deserializer/DDLY (falling edge-triggered cell ISERDESE2 clocked by dphy_hs_clock_p {rise@0.000ns fall@1.488ns period=2.976ns}) Path Group dphy_hs_clock_p Path Type Setup (Max at Fast Process Corner) Requirement 1.488ns (dphy_hs_clock_p fall@1.488ns - dphy_hs_clock_p rise@0.000ns) Data Path Delay 1.822ns (logic 1.822ns (100.000%) route 0.000ns (0.000%)) Logic Levels 2 (IBUFDS=1 IDELAYE2=1) Input Delay 4.250ns Clock Path Skew 1.372ns Clock Uncertainty 0.035ns I would like to request information as to how I may solve timing closure for the MIPI_D_PHY_RX. This is an unmodified project.