Tim S.

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  1. As an exercise in learning SystemVerilog 2012+, I authored a fourth rendition of this design, completely in SystemVerilog. https://github.com/timothystotts/fpga-serial-acl-tester-1 The project now has four designs: Microblaze AXI subsystem, completely Verilog-2001, completely VHDL-2008, and completely SystemVerilog 2012+. Regards, Tim S.
  2. I'd like to mention that within this project I designed in both VHDL-2008 and Verilog-2001 a Pmod SPI Mode 0 driver that enables design of a companion peripheral driver specific to the Peripheral device on the SPI bus. These two new diagrams may explain how pmod_generic_spi_solo.v or pmod_generic_spi_solo.vhdl, as well as the Peripheral driver coding style, can be reused for each SPI Pmod in the design. Regards, Tim S.
  3. Hi, I'd like to mention that I completed a first-draft of a VHDL test-bench / verification environment, for the Accelerometer Tester design previously announced. The VHDL test-bench is capable of executing with the free GHDL simulator on Linux or on Windows Subsystem for Linux. (The MSYS2 version of GHDL on Windows appears to crash.) Take a look. I created the beginning of models for the Pmod SSD (7SD), Pmod CLS, Pmod ACL2--according to my usage of them in my project. https://timothystotts.github.io/2021/01/08/vhdl-verification-of-fpga-serial-acl-tester-1-with-open-source-tools.html
  4. The 2020.2 release notes point to the following Xilinx Answer Record: https://www.xilinx.com/support/answers/66184.html
  5. The software driver Makefile for this module was updated to work with Vitis 2020.2 . See: https://github.com/timothystotts/vivado-library/branches branch zybo-z7-20-vivado-2020.2 or arty-a7-100-vivado-2020.2 Regards, Tim S.
  6. The source code and document for this project were updated from using Xilinx Vivado/SDK 2019.1 to Xilinx Vivado/Vitis 2020.2 .
  7. The source code and document for this project were updated from using Xilinx Vivado/SDK 2019.1 to Xilinx Vivado/Vitis 2020.2 .
  8. @flyingfork, The Release Notes document for each edition of Vivado / Vitis contains a section on System Requirements and System Prerequisits. The x86_64 and i386 libraries requiried for executing the DocNav and the toolchain are listed. It requires you to set a second dpkg architecture (i386) and install both x86_64 and i386 binaries of QT, GTK, and multiple others. I recommend following Xilinx's guidelines so that you don't have unexplained failures. Regards, Tim S.
  9. The Accelerometer Tester to execute on Zybo Z7 was updated from Vivado/SDK 2019.1 to Vivado/Vitis 2020.2 .
  10. This project was upgraded to Vivado/Vitis 2020.2 .
  11. This project was upgraded to Vivado/Vitis 2020.2 .
  12. This project was upgraded to Vivado/Vitis 2020.2 .
  13. This project was release for Vivado/SDK 2019.1, and then upgraded to Vivado/Vitis 2020.2 .
  14. Hi to the community. I have posted on GitHub an APSoC design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS. https://timothystotts.github.io/2020/09/14/hygro-sensor-readings-tester-on-zybo-z7.html Regards, Tim S.
  15. Hi to the community. I have posted on GitHub a FPGA design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS. https://timothystotts.github.io/2020/09/12/hygro-sensor-readings-tester-on-arty-a7.html Regards, Tim S.