Tim S.

Members
  • Content Count

    66
  • Joined

  • Last visited

About Tim S.

  • Rank
    Frequent Visitor

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Hi there. Last year I posted on GitHub two projects that implement communication with the Pmod ACL2, targeting the Arty-A7-100 and Zynq-Z7-20 respectively. The past two months I've updated these projects to the Xilinx Vivado 2021.2 with TCL scripts version controlled for recreation of the project and block diagrams. You can find the design refresh at: https://timothystotts.github.io/2021/11/26/refresh-of-the-fpga-accelerometer-tester.html and https://github.com/timothystotts/fpga-serial-acl-tester-3/ Note that there are five example Xilinx Vivado/Vitis projects that im
  2. As an exercise in learning SystemVerilog 2012+, I authored a fourth rendition of this design, completely in SystemVerilog. https://github.com/timothystotts/fpga-serial-acl-tester-1 The project now has four designs: Microblaze AXI subsystem, completely Verilog-2001, completely VHDL-2008, and completely SystemVerilog 2012+. Regards, Tim S.
  3. I'd like to mention that within this project I designed in both VHDL-2008 and Verilog-2001 a Pmod SPI Mode 0 driver that enables design of a companion peripheral driver specific to the Peripheral device on the SPI bus. These two new diagrams may explain how pmod_generic_spi_solo.v or pmod_generic_spi_solo.vhdl, as well as the Peripheral driver coding style, can be reused for each SPI Pmod in the design. Regards, Tim S.
  4. Hi, I'd like to mention that I completed a first-draft of a VHDL test-bench / verification environment, for the Accelerometer Tester design previously announced. The VHDL test-bench is capable of executing with the free GHDL simulator on Linux or on Windows Subsystem for Linux. (The MSYS2 version of GHDL on Windows appears to crash.) Take a look. I created the beginning of models for the Pmod SSD (7SD), Pmod CLS, Pmod ACL2--according to my usage of them in my project. https://timothystotts.github.io/2021/01/08/vhdl-verification-of-fpga-serial-acl-tester-1-with-open-source-tools.html
  5. The 2020.2 release notes point to the following Xilinx Answer Record: https://www.xilinx.com/support/answers/66184.html
  6. The software driver Makefile for this module was updated to work with Vitis 2020.2 . See: https://github.com/timothystotts/vivado-library/branches branch zybo-z7-20-vivado-2020.2 or arty-a7-100-vivado-2020.2 Regards, Tim S.
  7. The source code and document for this project were updated from using Xilinx Vivado/SDK 2019.1 to Xilinx Vivado/Vitis 2020.2 .
  8. The source code and document for this project were updated from using Xilinx Vivado/SDK 2019.1 to Xilinx Vivado/Vitis 2020.2 .
  9. @flyingfork, The Release Notes document for each edition of Vivado / Vitis contains a section on System Requirements and System Prerequisits. The x86_64 and i386 libraries requiried for executing the DocNav and the toolchain are listed. It requires you to set a second dpkg architecture (i386) and install both x86_64 and i386 binaries of QT, GTK, and multiple others. I recommend following Xilinx's guidelines so that you don't have unexplained failures. Regards, Tim S.
  10. The Accelerometer Tester to execute on Zybo Z7 was updated from Vivado/SDK 2019.1 to Vivado/Vitis 2020.2 .
  11. This project was upgraded to Vivado/Vitis 2020.2 .
  12. This project was upgraded to Vivado/Vitis 2020.2 .
  13. This project was upgraded to Vivado/Vitis 2020.2 .
  14. This project was release for Vivado/SDK 2019.1, and then upgraded to Vivado/Vitis 2020.2 .
  15. Hi to the community. I have posted on GitHub an APSoC design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS. https://timothystotts.github.io/2020/09/14/hygro-sensor-readings-tester-on-zybo-z7.html Regards, Tim S.