pcdeni

Hi, I have trouble instantiating a MIG and using the DDR on the NetFPGA SUME board. In the acceptance test, the init_calib_complete goes high, however I cannot recreat it in vivado 2020.1 The sources my configurations were based on: NetFPGA SUME live repository's multiple projects OSNT SUME live repository's extmem project Tapasco project. Additionally as the vc709 is similar, I have taken a look on the followings: https://www.youtube.com/watch?v=0KnvW_6Bgu0&ab_channel=XilinxInc https://www.xilinx.com/support/documentation/boards_and_kit

Hi, Does anyone know of a reference design or a board support package that works for the NetFPGA Sume board? I already tried to build the official github repo. Maybe missed something, as it didn't work for me, but another led blinking project (from github) seems to build in vivado. I would like to have a board support package including the memory interfaces and PCIe, does anyone know about such?

Hi, I am searching for an FPGA dev board with lots of available GPIO pins, but unfortunately I can not really find any. Almost all of the dev boards are made with unnecessary peripherals connected to it, or just extra (but small) memory and stuff, which takes away I/O. Or if neither is the case then, because of cost considerations, lower number of layers are used for the PCB, which makes it impossible to route all the GPIO pins. I would be surprised to see that nobody needs a good Xilinx 7th series based FPGA with as many GPIOs made available on pins as possible. (no, no LEDs,