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About gautam

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  1. Yes, I have seen in this 5 bit address for the channel selection. But the xadc_wizard block's DADDR[6:0] input is 7 bit. What are other two bits used for? Do they select minimum maximum values? If the other two bits can be ignored, then should the 5 bit address be left (MSB) justified or right (LSB) justified?
  2. I verified that the timing follows as in the ug480 xadc guide. I am now uncertain about my implementation of DADDR[6:0] address input in xadc wizard block. Is there any documentation or explanation on DADDR bus? The xadc guide only says “Address bus for the DRP.”
  3. Hi elodg, I see that all values are read correctly through the PS directly. When AUX inputs are supplied voltages I see the same values when I read through PS directly in software. The temperature values are not the same on the DRP interface, it is always around 2degrees higher that the PS read values. The VP VN is always 0 on DRP, whereas the even AUX input (AUX6, AUX14) registers give 0x5999 and odd AUX input (AUX7,AUX15) registers give 0x5111. The test were conducted with both mode selection jumper connected to SD card as well as with this jumper completely removed. I can also see the correct values on the system monitor dashboard in vivado as below (The temperature reading matches with the DRP read values): The equivalent DRP output is as seen below: Is there something I am missing? Are there any other test I can perform to troubleshoot this issue?
  4. Hi there, I have been not having luck in reading the aux pins on the zybo z7 board. I have setup the system as below: The XADC is setup with DRP and channel sequencer in continuous mode, with the setup as below: I can read the voltages on the XADC system monitor dashboard as below: But the XADC only read 0x5999 on Aux 15 Pin, as seen below: As you will see above, Aux 6 and Aux 14 is stuck at 0x5999 and Aux 7 and Aux 15 is fixed at 0x5111. I don't get any errors only a critical warning: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. I have been debugging this for two days now and I am unable to fix this issue. So any help to get the analog inputs on aux pins converted is greatly appreciated! Cheers, Gautam.
  5. Thanks @morsucci, Some kind of reference like this was what I was looking for. This will keep me busy for sometime.
  6. Hi @jpeyron, I don't mind accessing the Pmod NIC100 directly through the SPI interfaces available for the ARM processors on the Zynq chip rather than going through the FPGA. So I assume that I would not need an IP core for SPI and enc424j600. I have enabled (as lkm) the encx24j600 driver available in the zynq linux kernel. Now that I have the following device tree for SPI1, I need to know what to add inside this tree to bind the encx24j600 driver to the enc424j600 chip on the Pmod NIC100: spi1: [email protected] { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; Let me also know if there is a different way to bind the encx24j600 driver to the Pmod NIC100 chip over SPI1 interface.
  7. Hi Guys, My application on linux requires two ethernet ports on the Zybo Z7 board. So I have recently bought a Pmod NIC100 card. I read the references and I have enabled the encx24j600 driver in the xilinx linux kernel. I have enabled SPI0 controller in vivado for the Z7 board. Correct me if I am wrong, but I reckon to use the enabled encx24j600 driver, I have to add the interrupts and registers under spi parent in the device tree but I don't know the specifics of what I have to add. Can someone please help me out? My intention is to get this board to appear as eth1 in xilinx linux. I would appreciate any other way than device tree method to do this as well. Let me know if you need any other information.
  8. Hi Guys, I design and commission robots and motion control systems. I am interested to go low level in the design by using fpgas. I look forward to talk to you guys and get help to get there.