Mike Placke

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  1. We are using several copies of the JTAG-HS3 programming cable in our lab to load programs to a Xilinx Ultrascale+ device using Vivado via JTAG. Sometimes we can load at 15Mhz clock speed and succeed, sometimes we must cut back to 10MHz to be successful, and sometimes even 7.5MHz when dealing with the same board at different times. Since it is a big program into a big part, higher speed matters. We have tried the standard cable wiggling and swapping cables, but still have not found consistency. Is there some issue that others have seen, updates that need to be applied, or anything else that may explain the variability? Any feedback appreciated. Thanks. Mike Placke