sosso

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  1. sosso

    nexys video QSPI flash

    Hi everyone, Please, I'm looking for the use of the QSPI_flash Ip in vivado, I think we use it as an interface between the QSPI flash memory and the soft processor( microblaze for my case), whereas the QSPI flash memory is used to store the bitstream, how does this create the QSPI flash IP whereas the bitstream which is used to create the IP is stored in the QSPI flash and this same IP is used as an interface? thank you so much
  2. sosso

    OLED nexys video

    hi JColvin, Thank you so much, how do we call the distance in which two lines of character are written?, I mean there is the cursor which moves from the first to the second line,and there is a cursor which moves between pixels ( find it in the libraries controling the oled), I need the term for my dissertation, how can I express that ? thank you
  3. sosso

    OLED nexys video

    hi everyone, Please i'm looking for informations about the nexys video OLED, how many characters can we write in the horiz and vert axes? can we modify the size of a character? can we use character when we speak about the oled writing area capability? thank you so much
  4. sosso

    petalinux

    Hi everyone, I'm intereseted in petalinux because I want to do simulation of microblaze based system, but the definitions and documentations I find in the internet is quite faint, qo my question is what can we do with petalinux , what exactly can we do with QEMU and what kind of simulation can we do with it ? ( please try to differ from the documentation of the internet, and please explain with your most simple words ) thank you soooo much in advance
  5. sosso

    nexys video memories

    D@n, Yes, so my problem is what is the role of the DDR ram? thanks you
  6. sosso

    nexys video memories

    hi everyone, in the Nexys Video, there is two external memories, please correct me if I'm wrong : --The QSPi,is the memories which stores the configuration ( FPGA bitsream is the way to configure to create the block design) of the FPGA to make our block design. -- The DDR3 is used as a memory which stores what the results of what is going on. works as a RAM in a PC -- the cache memory, which is created after inserting the bitstream stores the instructions and data of the program.
  7. Hi jpeyron, I tried to use the sdk, the functions used in vivado sdk of 2016.4 are different from 2017.4 ?
  8. hi jpeyron, I removed vivado 2017.4 and replaced it with 2016.4, it works perfectly , no errors, no latency during synthesis nor in implementation, much faster than 2017.4, I think I dindn't install very well the 2017.4, and it was so slow, so thank you so much for you precious help , do I have to put this subject as solved?
  9. hi jpeyron, 4 GB of ram, now i tried the small tuto you adviced me , without oled without qspi implemented, It's been an hour since I runned the synthesis, It didn't finish yet
  10. hi jpeyron, Is it normal that the synthesis take too much time, sometimes more than an hour, I have an i3 intel processor, ?
  11. Hi jpeyron, thanks a lot, I'm downloading it now, is there any difference I have to be aware of ?
  12. Hi jpeyron, i'm using vivado 2017.4, I'm following the exact same steps but it does not generate the same block design as shown on the tuto
  13. hi jpeyron, here is the block design : I tried both, when implementation to parameter some feature concerning the bitsream, the frequency of 33 mhz .. , and I tried also not doing anything but it doesn't work? thank you
  14. hi jpeyron thank you so much that helped a lot, the implementation works , but now I get problems in the bitsream, i get errors while generating bitstream ? here is one of the messages: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 66 logical ports use I/O standard(IOSTANDARD) value "Default", instead cause I/O contentiojn or incompatibilty with the board power or connectivity affecting performance .....
  15. hi jpeyron, --[Vivado_Tcl 4-16] Error(s) found during DRC. Router not run. --[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 400.000 MHz (CLKIN1_PERIOD, net clk_out1) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y3 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (10.000000), multiplication factor CLKFBOUT_MULT_F (4) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device. ---[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 400.000 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y3 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (20.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.