BYTEMAN

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  1. Like
    BYTEMAN reacted to JColvin in Cmod A7-35T: UART Lite with interrupt AXI interrupt and Generic Interrupt question   
    Hello @BYTEMAN,
    Taking a look at this thread, you may need to re-generate your BSP sources, or potentially delete it and create a new one. I would also make sure that all of the SDK settings (I'm not certain if you have changed any) are on their default settings.
    Thanks,
    JColvin
  2. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Quad SPI memory question and peripheral interfacing   
    Hi @BYTEMAN,
    I verified that on my cmod A7 project i was able to re-program the elf(step 4.1) on the flash without having to re-program the download.bit into flash(step 4.2).  I will point this out to out content team as well so they can confirm while updating/fixing the sdk flash tutorial.
    thank you,
    Jon 
  3. Like
    BYTEMAN reacted to JColvin in Cmod A7-35T: UART Lite with interrupt AXI interrupt and Generic Interrupt question   
    Hi @BYTEMAN,
    I'm not certain on the differences between the two interrupt controllers, you will likely need to contact Xilinx to see if they have any additional thoughts or concerns on this.
    As for the SDK debugging behavior, according to this Xilinx site, the GDB mode is depreciated, so you will likely want to instead use the "Launch on Hardware (System Debugger)" option instead for some better results, as this Xilinx forum thread seems to indicate as well.
    Thanks,
    JColvin
  4. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Quad SPI memory question and peripheral interfacing   
    Hi @BYTEMAN,
    My understanding is we are trying to get a 3 MHz clock as shown on page 8 of the Using SPI Flash with 7 Series FPGAs. This accomplished by this (ext_spi_clk frequency) / (frequency ratio parameter) = (clock output frequency)  ie. if FR is 16x1 and ext_spi_clk is 50MHz, then the actual spi clock will run at ~3MHz. The pins for the qspi are in the part0_pins.xml file of the Cmod A7 board files which are also reflected in the xdc file here.
    thank you,
    Jon
  5. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Quad SPI memory question and peripheral interfacing   
    Hi @BYTEMAN,
    I get these errors in the newer versions as well. These errors do not effect the project.
    thank you,
    Jon
  6. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Quad SPI memory question and peripheral interfacing   
    Hi @BYTEMAN,
    Here is a verified and completed project for the Cmod A7 in vivado 2017.4 that puts a slightly altered hello world template (i put the hello world printf in an infinite while loop) into the flash using sdk. I compressed the bitstream but did not comment out the verbose code. As you mention above you can also skip step 2.3 since there is no DDR.  
    I have also talked with the content team about the discrepancies in the tutorial. It is on their list to fix/update. They also agree that your thought process for how thing work for the qspi is as far as we can see accurate. 
    thank you,
    Jon
  7. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Quad SPI memory question and peripheral interfacing   
    Hi @BYTEMAN,
    In the case of the Cmod A7 there is not a mode jumper. You are correct that these tutorial were initially made for the arty. I believe your #2 statement sounds correct. I will confer with our content team on how we want to deal with this difference in regards to the tutorial.  Tomorrow i will make, verify and post on this thread a cmod A7 flash project for you to reference from.
    cheers,
    Jon
  8. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Quad SPI memory question and peripheral interfacing   
    Hi @BYTEMAN,
    The Cmod A7 Programming Guide shows how to program the Cmod A7  flash with a project not using microblaze. The How To Store Your SDK Project in SPI Flash tutorial shows how to program the flash using microblaze and the quad spi flash(ext_spi_clk on the ip core needs a 50 MHz clock from the clocking wizard).  if you need to use an external peripheral different than the on board memory (like a serial DAC) you would use one of the axi ip cores depending on the type of communication the serial DAC is using i.e. spi, i2c, uart, gpio. You would set the physical FPGA outputs for it through the XDC filles, e.g. using some pio pins. We have many different examples in our vivado library of how we facilitated the different communication along with sdk code to use the different pmods. We abstract a lot of the communication complexity from the hardware side of the design using the pmod bridge and the board files. If you are trying to learn how to use the axi quad spi ip core I would first start by looking at the AXI Quad SPI v3.2 LogiCORE IP Product Guide.
    thank you,
    Jon
  9. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Microblaze design and output pins   
    Hi @BYTEMAN,
    I am not aware of a way to have those specific microblaze configuration pages to be used after the initial block automation. I would suggest to reach out to xilinx about this question. I believe you are correct about the xdc overriding the board file defaults.
    thank you,
    Jon
  10. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7-35T MICROBLAZE INTERFACING WITH FABRIC LOGIC   
    Hi,
    one hint: "regular" AXI is fairly complex and achieves its performance by writing bursts. AXI-Lite is in comparison very simple but limited to writing only a single value at a time (which is usually what I want).
    With a 667 MHz Zynq and the simple example I posted earlier, a single write takes about 0.5 microseconds (a for-next loop counting down from 2M writing a constant to the bus takes one second, give or take some). I wonder how a microblaze (at 100 MHz) will perform.
    "Polling" is one approach - repeatedly check, whether new data is available. In more complex systems, interrupts would be used, opening up a pretty standard but still XL-size can of worms...
  11. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Microblaze design and output pins   
    Hi @BYTEMAN,
    Reading through your post i do not see an issue with your process for making external pins and constraining them with the xdc. In regards to the reset pin I reached out to one of our design engineers about this and they responded that the oscillator on the CmodA7 always runs so there is no way to stop or reset the input clock. If you want to reset the clock in a MicroBlaze design then you need to connect the reset pin of the MMCM block to an external pin, such as BTN0 or BTN1.
    They typically tie the clock reset pin of the MMCM block to a constant in my MicroBlaze block designs. It’s either a constant ‘1’ or a constant ‘0’, depending on what the active state of the Reset is configured for.
    You can see how we configured the microblaze for the cmod a7 35t by looking through the board files here. After you do block automation you can customize microblaze to your needs. The preset for microblaze that the board files facilitates configures microblaze for the cmod a7 so altering the setting can make issues with your design.
    thank you,
    Jon
     
  12. Like
    BYTEMAN reacted to artvvb in Cmod A7-35T MICROBLAZE INTERFACING WITH FABRIC LOGIC   
    @BYTEMAN
    My only major concern with the your current flow is that it is still relatively difficult to gain access to any control signals you might want to use. The Language Template GUI (which you can find in the Project Manager section of the Flow Navigator) has some boilerplate code for an AXI port map with customized parameters that you can add to your custom module. THis doesn't come with the actual AXI control template, but combining the syntax for the portmap with the IP you've created, you should be able to create the same design with only a single added module. AFAIK, added modules don't play as nicely with Connection Automation as actual AXI IP, but it may warrant some investigation.
    I am currently away from a PC with Vivado installed, so I am unfortunately unable to be more specific on where in the Language Templates you can find this...
     
    I'd suggest you try the above, but another method that can be useful to move data between Microblaze and HDL would be to use an AXI Stream interface (which is MUCH simpler than full AXI, there's some info in Xilinx UG761, starting at page 45) in your HDL module that connects to the transmit stream of an AXI4-Stream FIFO Controller (Xilinx PG080). I've been playing around with this a bit recently, and it seems like it works pretty well. This method is more useful for "bursty" data streams (Xilinx uses this for Ethernet communications), rather than "set and forget" registers (like LEDs or something), either on the processor or module side, but it's worth pointing out.
    Thanks,
    -Arthur
  13. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7-35T MICROBLAZE INTERFACING WITH FABRIC LOGIC   
    ... of course, a ready-made AXI GPIO might be just as good.
  14. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7-35T MICROBLAZE INTERFACING WITH FABRIC LOGIC   
    Check out the AXI GPIO. For simple designs, it may be all you need.
    On the other hand, putting my own logic on the bus allows some elegant solutions like read-sensitive registers that may simplify the software greatly. Digitop design has its own little team in larger projects (at least on ASIC), don't expect this to just fall into place.
    Maybe someone else can comment on "standard way", those are just paths I figured out for myself.
  15. Like
    BYTEMAN reacted to artvvb in Microblaze inputs   
    Welcome to the forum!
    How you do this depends on the internal logic you want to read. Could you explain a little more about your project?
    There are two primary ways for MicroBlaze to interact with internal logic:
    First, via an interrupt controller. This is only used to trigger MicroBlaze to do something based on a single bit flag.
    Second, via an AXI interface. This is likely what you will need. There are a couple of ways to do this, but my suggestion, at least to start with, would be to connect your internal signals to the gpio_io_i port of an AXI GPIO controller. Note that if your signals change frequently, or you can't just poll the signals, then you will likely need a proper AXI interface.
    Thanks!
    Arthur
  16. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7-35T Missing CFGBVS and CONFIG_VOLTAGE Design Properties   
    Hi,
    I'm 99 % certain that the problem is caused because you specify a clock twice: Once in the constraints file, once in the frequency setting of the clocking wizard.
    Solution: remove the constraints for clock frequency on the input pin.
    If you look closely, you'll see that the "Inter"-clock error ("from one clock to the other") relates to two clocks on the same signal, that is clk_out_2_clk_wiz_0 with a suffix that identifies the clock. In my understanding, this makes more sense when clocks are switched / gated (which you don't do).
    The constraint is meaningless and creates an impossible situation for Vivado, which it tries to resolve at best effort. Screwing up the rest of the design => failure to close timing.
     
    BTW, the setting in the clocking wizard that controls the auto-generated buffer is under the "Clocking options" tab (which is for some reason the 2nd one in your screenshot).
    Section "Input clock information" Input clock: Primary. Change "Source" from "single ended clock capable" to "No buffer". This is taken from clocking wizard 5.4 on an Artix.
     
     
     
  17. Like
    BYTEMAN reacted to JColvin in USING VIVADO IP CLOCKING WIZARD WITH THE Cmod A7-35T   
    Hi @BYTEMAN,
    Feel free to put up your dropbox link to your project if you so wish; I know we had communicated about this earlier, but for the interest of letting other users know that they may put dropbox links or google drive or something similar links to their project if the Vivado project gets too big to upload. Alternatively, pictures can be uploaded via the Gallery which doesn't have the same upload restrictions as putting the image directly into the post.
    Thank you,
    JColvin
  18. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7-35T Missing CFGBVS and CONFIG_VOLTAGE Design Properties   
    Do you maybe use a different Vivado version than I do (2017.4 here)? I don't have the "Board" tab at all, maybe because I didn't include any CMOD A7-specific files for this project.
    I'd comment it out in constraints
    >> Tthen I've to remove this constraint row from my XDC?
    (yes, this line).
    If that doesn't help, create a new project from scratch based on the FPGA type (not any board setup file).
    There is also an odd error message on the right behind your last screenshot... board_part file invalid?
  19. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7-35T Missing CFGBVS and CONFIG_VOLTAGE Design Properties   
    I suspect things will make sense if you connect the clock input pin only to the MMCM's input, without other connections to the net.
    Most likely, the IO can only drive a single clock-net buffer at the pin site, but you're trying to drive two. For that, the signal needs to go to the fabric => DRC 23-20 (theory!).
    Note, if you're using default MMC settings, "clk_div_inst" will include its own clock buffer. This can be disabled on the first page of the clkWiz IP configuration page (bottom right corner).
    If I had to measure jitter on the input clock per my own suggestion, the easiest way might be to simply build a 2nd bitstream
     
  20. Like
    BYTEMAN got a reaction from xc6lx45 in Cmod A7-35T Missing CFGBVS and CONFIG_VOLTAGE Design Properties   
    Dear All,
    I need to use inside the FPGA the 12 MHz clock, hence I've uncommented this two rows on the XCF file provided by Digilent.
    ## 12 MHz Clock Signal
    set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
    create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
    after that I've did the sysnthesis, my VHDL code is the following one:
    library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity led is Port ( btn : in STD_LOGIC_VECTOR(1 downto 0); led : buffer STD_LOGIC_VECTOR(1 downto 0); sysclk : in std_logic -- system clock 12 MHz ); end led; architecture Beh_arch of led is signal btn0s : std_logic; signal btn1s : std_logic; signal led0 : std_logic; signal led1 : std_logic; begin -- button clock synchr synch_input : process (sysclk) begin if sysclk'event and sysclk = '1' then btn0s <= btn(0); btn1s <= btn(1); end if; end process synch_input; -- led toggle with the button synch_toggle_leds : process (sysclk) begin if sysclk'event and sysclk = '1' then if btn0s = '1' then led0 <= not led(0); end if; if btn1s = '1' then led1 <= not led(1); end if; led(0) <= led0; led(1) <= led1; end if; end process synch_toggle_leds; end Beh_arch; what I try to do is a simple toggle of the led when the button is pressed, countinuosly toggling at the clock frequency.
    All the process going straight but on the final report I see a warning:
    [DRC 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
     set_property CFGBVS value1 [current_design]
     #where value1 is either VCCO or GND
     set_property CONFIG_VOLTAGE value2 [current_design]
     #where value2 is the voltage provided to configuration bank 0
    Refer to the device configuration user guide for more information.
    I've did some search and I found this:
    https://www.xilinx.com/support/answers/55660.html
    someone could you please give me some other explanation? What should be the exact settings to use for this board:
    - Configuration voltage: 1.5 / 1.8 / 2.5 / 3.3
    - Configuration bank voltage selection: GND or VCCIO
    where I can found this specification for the FPGA used? Datasheet I think but what parameters?
    ----
    I've noticed the last row "Refer to the device configuration user guide for more information" then found the UG470 (v1.12)  at page 21 and 24 Table 2-4 there are some infos.
    Searching for the pin-label file give me ()
    V9 and G12 -> VCCO_0
    V11 -> CFGBVS_0
    After that searching on the electrical schematic give me:
    3.3 V VCCO_0 (page 4/7)
    3.3 V CFGBVS_0 (page 2/7)
    Then following these data, the correct settings should be as into the attached figure (select first the Syntesis tab into the left side of the Vivado main window then into the main Vivado menu bar select Tools tab and finally the Edit Device Properties menu). After that the warning disappear and the board is also running correctly as before the warning :).
    Someone can confirm?
    Thanks!
    Best regards
     
     

  21. Like
    BYTEMAN reacted to jpeyron in Cmod A7-35T Missing CFGBVS and CONFIG_VOLTAGE Design Properties   
    Hi @BYTEMAN,
    The easiest way to get the 12 mhz clk would be to use the clocking wizard. Here is a project that uses the clocking wizard with VHDL that you can use as an example for using the clocking wizard.
    cheers,
    Jon
  22. Like
    BYTEMAN reacted to JColvin in Warning [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25...   
    Hi @BYTEMAN,
    These warnings are because when you installed the Vivado software, the support materials for the Spartan 7 chips (not available for Vivado 2016.X) nor the Kintex 7-series chips were installed alongside the Artix-7 series FPGA chips. As you are not creating a project for either of those chip series, you can safely ignore them.
    Let me know if you have any other questions.
    Thanks,
    JColvin
  23. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7 oscillator question   
    PS: Reading the above post:
    I suggest you DO use the IP wizard, not calculate it manually. Pain does not equal gain.
     
  24. Like
    BYTEMAN reacted to JColvin in Cmod A7 oscillator question   
    Hi @BYTEMAN,
    The Oscillator section that you were looking for before is available here: https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual#oscillatorsclocks.
    Thanks,
    JColvin
  25. Like
    BYTEMAN reacted to xc6lx45 in Cmod A7 oscillator question   
    Hi,
    On the first page on the clocking Wizard IP config, switch to "MMCM" mode. That will accept 12 M input frequency.
    E.g. "Project manager" window, "IP catalog", search for "clock", double-click "clocking wizard", then set "Primitive" on the first page to "MMCM" instead of "PLL".
    Unfortunately, my quota is exhausted, otherwise there would be a screenshot