M. Betz

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  1. Hi, You are right, both methods work, I was just able to confirm it with a scope. To wrap it up, one way is to add this to the .xdc file: set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { qspi_sck }]; The other way is to use this primitive: STARTUPE2 #( .PROG_USR("FALSE"), .SIM_CCLK_FREQ(10.0) ) STARTUPE2_inst ( .CFGCLK (/* NC */), .CFGMCLK (/* NC */), .EOS (/* NC */), .PREQ (/* NC */), .CLK (1'b0), .GSR (1'b0), .GTS (1'b0), .KEYCLEARB (1'b0), .PACK (1'b0), .USRCCLKO (SPI_CLK), .USRCCLKTS (1'b0), .USRDONEO (1'b0), .USRDONETS (1'b1) ); Thanks jpeyron and D@n for your quick help! Cheers Michael
  2. Hi, thanks for the quick response! I didn't know about the STARTUPE2 primitive, which seems to be exactly what I need. I'll give it a shot and let you know. Cheers Michael
  3. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers Michael Betz