Michael2018

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  1. Attache ZEDBoard configuration screen shot and I did select the ZEDBoard file. Uart 1 is selected. Do you think " Xil_out 32 " error message is due to driver missing? this example is on the Michael
  2. Hi: Jon thank you for your responds. Uart is configured but I am not sure if it connected by ZEDBoard file. If you follow the book instruction created a constraint file, there is no connection for Uart port. but in zybo board file, there is connection with Uart/Jtag pin. Michael
  3. Hi: Jon I tried both zedBoard and zybo board. I got same results. I don't get error message when I import "bsp" file. Only time when I import "led_controller_test_tut_4A.c" file do you think that is Vivodo software issue ? Please take a look attached file. thank you very much for your help! Michael xilinx.com_user_led_controller_1.0.zip
  4. Hi: JON I regenerate the bps source but there is same error message. hover the x I get same information. Pleas help me figure it out. thank you Michael
  5. I am working on the Zynq book tutorial book Exercise 4A after I imported " led_controller_test_tut_4A.C " file. I got error message " Underfined reference Xil_out 32" Please any one has same error? please help find solution. Michael
  6. Hi: Jon I did not do any modification for processor IP. just default set up. I will take a look the zynq book and hope find some clue. thank you for your help and you have a greate weekend! Michael
  7. when I ceate a warrper file I got warring message: Analysis Resultssources_1[filemgmt 20-1318] Duplicate Design Unit 'zynq_interrupt_system_ps7_0_axi_periph_0' found in library 'xil_defaultlib' sim_1[filemgmt 20-1318] Duplicate Design Unit 'zynq_interrupt_system_ps7_0_axi_periph_0' found in library 'xil_defaultlib' zynq_interrupt_systemvalidate_bd_design [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. do I need fix it? How to fix it Sincerely, Michael
  8. Hi: Jon when I create a new design with zynq processor I got warring messaage : validate_bd_design [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. can you tell me what is wrong? and How to fix it. thank you very much Michael
  9. Hi: Jon every thing is working now . just board file is in correct. After I change it B.3 version. It work fine. thank you very much for your help! specially thank you for your quick responds. Sincerely, Michael
  10. Hi: Jon I updated the Board file to B.3 right now different looking when I look the zynq IP configuration window. but when I run at SDK at Hello project, the terminal thing print out; here some log file: 15:06:19 INFO : Registering command handlers for SDK TCF services 15:06:20 INFO : Launching XSCT server: xsct.bat -interactive C:\Data\Project\Hello2\Hello2.sdk\temp_xsdb_launch_script.tcl 15:06:22 INFO : XSCT server has started successfully. 15:06:22 INFO : Successfully done setting XSCT server connection channel 15:06:22 INFO : Successfully done setting SDK workspace 15:06:22 INFO : Processing command line option -hwspec C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper.hdf. 15:07:43 INFO : Connected to target on host '127.0.0.1' and port '3121'. 15:07:45 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo 210279573175A" && level==0} -index 1' command is executed. 15:07:46 INFO : FPGA configured successfully with bitstream "C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/hello2_wrapper.bit" 15:10:32 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo 210279573175A" && level==0} -index 1' command is executed. 15:10:32 INFO : 'fpga -state' command is executed. 15:10:32 INFO : Connected to target on host '127.0.0.1' and port '3121'. 15:10:33 INFO : Jtag cable 'Digilent Zybo 210279573175A' is selected. 15:10:33 INFO : 'jtag frequency' command is executed. 15:10:33 INFO : Sourcing of 'C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/ps7_init.tcl' is done. 15:10:33 INFO : Context for 'APU' is selected. 15:10:33 INFO : Hardware design information is loaded from 'C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/system.hdf'. 15:10:33 INFO : 'configparams force-mem-access 1' command is executed. 15:10:33 INFO : Context for 'APU' is selected. 15:10:33 INFO : 'stop' command is executed. 15:10:33 INFO : 'ps7_init' command is executed. 15:10:33 INFO : 'ps7_post_config' command is executed. 15:10:33 INFO : Context for processor 'ps7_cortexa9_0' is selected. 15:10:33 INFO : Processor reset is completed for 'ps7_cortexa9_0'. 15:10:33 INFO : Context for processor 'ps7_cortexa9_0' is selected. 15:10:33 INFO : The application 'C:/Data/Project/Hello2/Hello2.sdk/Hello_ledSwitch2/Debug/Hello_ledSwitch2.elf' is downloaded to processor 'ps7_cortexa9_0'. 15:10:33 INFO : 'configparams force-mem-access 0' command is executed. 15:10:33 INFO : ----------------XSDB Script---------------- connect -url tcp:127.0.0.1:3121 source C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/ps7_init.tcl targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0 loadhw -hw C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/system.hdf -mem-ranges configparams force-mem-access 1 targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0 stop ps7_init ps7_post_config targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0 rst -processor targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0 dow C:/Data/Project/Hello2/Hello2.sdk/Hello_ledSwitch2/Debug/Hello_ledSwitch2.elf configparams force-mem-access 0 ----------------End of Script---------------- 15:10:33 INFO : Memory regions updated for context APU 15:10:33 INFO : Context for processor 'ps7_cortexa9_0' is selected. 15:10:33 INFO : 'con' command is executed. 15:10:33 INFO : ----------------XSDB Script (After Launch)---------------- targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0 con ----------------End of Script---------------- 15:10:33 INFO : Launch script is exported to file 'C:\Data\Project\Hello2\Hello2.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_hello_ledswitch2.elf_on_local.tcl' please tell me what is not right. Michael