Geralt

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  1. The normal ZedBoard (bigger size than MicroZed) also provides those expansion connectors, right? Do they have a specific name (e.g. FMC)? Thanks @all so far!
  2. Do you know if the Zybo board provides any additional GPIO connectors apart from the Pmod ports? The ZedBoard has an FMC connector in addition to the Pmod connectors but the Zybo does not seem to have anything apart from Pmod. As I wrote in the previous post: Higher rates for data transfer and sufficient RAM for buffering if there is latency (or breaks in writing cycles on the SD card) in the data transfer. Unfortunately, you have far less peripherals than on MCUs.
  3. Hello! In the hardware user's guide of the ZedBoard I read the following: "Four Pmod connectors interface to the PL-side of the EPP. These will connect to EPP Bank 13 (3.3V). One Pmod, JE1, connects to the PS-side of the EPP on MIO pins [7,9-15] in EPP MIO Bank 0/500 (3.3V). Uses for this Pmod include PJTAG access (MIO[10-13]) as well as nine other hardened MIO peripherals (SPI, GPIO, CAN, I2C, UART, SD, QSPI, Trace, Watchdog). Two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed differentially to support LVDS running at 525Mbs." My ques
  4. I thought that this would be an easy part. I have not worked with these boards and ADCs before (mostly with microcontrollers) but I thought that you simply send a "start of conversion" signal to any ADC, external as well as internal. Or you keep those ADCs running continuously and just sample the output registers with the desired sampling frequency. I do not have an idea which problems you are addressing in your post. The only reason why I considered the Zynq-7000 boards is that some colleagues already programmed them and have a bit experience with them. First we wanted to use a microc
  5. Thanks for the hint. That is why I discarded the Python (PYNQ-Z1) approach. I will now consider using one of the ZedBoards/MicroZed/Zybo. I think they provide a lot more flexibility and overhead in terms of connectors and computational power. Of course you can never achieve "simultaneous" sampling. There is always some nanoseconds delay/difference. At some point you even have to consider the signal propagation of the clock or convert signal over the PCB conductors. But I think if we use separate ADC peripheral boards and those two XADCs, we could firstly solve the problem of inter-chan
  6. Thank you very much for the answers! So the XADC can sample up to 8 different signals per ADC. Because it is dual that would result in 16 different signals maximum. But because of the interleaved sampling (one signal after another) you would not reach 1 MSPS, but only 1/8 MSPS (but two signals sampled simultaneously each time). Did I get that right? So if I would need to sample all the six analog signals simultaneously, I could use the two XADC modules and four additional ADC cards that I connect at those Pmod ports of the development board. That should work, right? Do you kno
  7. Hello! Me and my colleagues want to do a project and we are thinking about using one of the various development boards with Zynq-7000 for that purpose. Basically we just want to sample and measure some signals and transfer them to a PC (preferably via gigabit-ethernet) for evaluation. So the Zynq would have to do a real-time hardware-in-the-loop task. The signals we want to measure are as follows: 3 analog signals sampled @ 1 kHz by an ADC 3 analog signals sampled @ 100 kHz by an ADC 2 incremental encoders the frequency of a quadrature pulse signal (we would ne