Mahdi

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  1. Hello, I am using a Pmod Grove RTC with a PYNQ board, and it seems to be operating normally when it is powered directly from the 3.3 V of the board. However, when I plug in the backup battery (3.0 V CR1225) into the grove RTC and have it also connected to the board, I can not read or write to the clock. It seems the backup battery somehow disables the device. After reading the page 3 of datasheet of the DS1307 chip, I noticed something weird: "DC power is provided to the device on these pins. VCC is the +5V input. When 5V is applied within normal limits, the device is fully accessible an
  2. Hello, I have got a Pmod grove RTC which I hoped to be able to use it the same way I have been using my Pmod Grove IMU (using the example C code that is provided here), however I noticed there is no such example code for the Grove RTC. I am aware of the Arduino and python scripts that are available on Grove RTC webpage, but due to some limitations I need to use it the same way I am using Grove IMU device (which is using it with PYNQ board). Does anybody know if there is such example code written in C language for this device out there that I can use? It seems to be a simple I2C device, howe
  3. Hi @kwilber Using Linux to multi thread my application is similar to the behavior I am trying to duplicate with my bare-metal application, but I am worried the overhead of full Linux OS will cause more problems with meeting my data throughput requirements. If it is possible to share memory between Linux and a bare-metal application and has been done already, why is it so difficult to do it with two bare-metal application? I just do not find a useful tutorial on how to do this. Mahdi
  4. Hi @jpeyron I looked at the link you shared, but it does not seem to share DDR memory between the two cores at all. Each application runs on a single core independent of the other one and has its own dedicated memory. Thanks for sharing it anyway. Mahdi
  5. Hello, I am wondering what is the best way to share a big chunk of memory between two cores of Arty-Z7-10? Note that I have already gone through the XAPP1079 of Xilinx, however this tutorial does not really share the DDR memory between two cores. It only uses OCM to share a semaphore between two cores, so two cores can share the terminal. To give you more detail on what my goal is: I want to read a big chunk of data (something in oder of 15 - 30 MB) on CPU#0 and put that into DDR memory, and then let the CPU#1 know when I am done via a flag (which I know how to do with OCM). Followin
  6. Hi @jpeyron I looked at the link you shared and if it is true what it says, I can only access the SD slot through SDIO controller when enabled through MIO. Does this mean that I can not control the SD card using a Verilog source code and I have to communicate with it only on PS side? My question is exactly similar to the forum you shared. I am trying to access SD slot on-board of Arty-Z7 on the PL side, rather than PS side which is normally what people do. I used the PmodSD because I did not know how to get the on-board SD slot to work and PmodSD was for testing. At the end, my purpo
  7. Hi @jpeyron I have been looking at the references provided and had some success communicating with a PmodSD using a modified version of the code from the MIT website. However, I am having difficulty interfacing this code with the on-board SD card slot. What is confusing is that the SD input/output ports on the ZYNQ are split when exposed through EMIO. Do you have any recommendation on how to interface with the EMIO ports directly? Thanks, Mahdi
  8. Hi @jpeyron Thanks for the suggestion. I managed to successfully use the Cora-Z7-10 project with Arty-Z7-10 board and did some tests by feeding a sinusoidal signal into different channels of ADC. Here are my observations: This project uses the buttons to select active channels of ADC, so I started with having Vp-Vn active and monitored the voltage in SDK terminal. During this test, I observed similar voltage at SDK terminal compared to input terminal, and all of single ended pins (A0-A5) were inactive, except A3 which was showing about 30 mV. This means that even though A3 was not ac
  9. Hi @jpeyron Thanks for your response. I am aware that in this case the two switches are only connected to two channels. My goal is to get this to work with 3 channels eventually. I did some experiments by feeding a 1 Hz, 400 mV sinusoidal signal with 0 V offset into three differential channels of Arty using a function generator and here are my observations. When both switches are high, and signal is going through 1st differential channel (V_P and V_N pins), I see the LEDs blinking with 1 Hz frequency. If I connect the signal to the 2nd (A6-A7) and 3rd (A8-A9) differential channe
  10. Hello, I am using the latest version of XADC demo for Arty-Z7-10. In this demo, two switches should enable two XADC channels to be read from, however all of ADC channels (A0 to A11) are active together at the same time for different switch configurations which makes me think there is cross talk between these channels or XADC demo code is broken. Have anybody experienced this? I need to have three independent active ADC channels, while I have been able to use only one of them due to this cross talk issue. Best, Mahdi
  11. Hello, I am trying to develop a simple verilog code on Arty-Z7-10 that writes to the SD card on the PL side, without having to use SDK software. To do so, I believe I need to setup my SD card pins as EMIO in the ZYNQ and modify the constraint file to uses correct pin mapping. However, I wonder if anyone has done such type of coding before and is able to provide me with more detailed information. I found this tutorial which has tried to do same thing with SPI, but it was not very detailed. https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part193
  12. Hello, I am working on a dual core project with mailbox IP on a Arty Z7-10 board which has been acting inconsistently. In my project, 1st core is receiving data from FPGA and sending it through mailbox to the 2nd core; the 2nd core is supposed to receive and write them to the SD card. I need to write the data at 0.5 to 1 MB/s speed, so I can not read and write fast enough on one core. As an example to show the problem, I am writing a number to the card that is being incremented by one on a loop, and plot that versus the clock cycles. Supposedly, my output should look like a straight
  13. Hi @jpeyron I have good news. Since you insisted on having the delay, I went ahead and re-tested my code again. I filled up my code with delay functions and started to remove them one by one to see where it breaks, and eventually was able to figure out how much delay is needed and where it should be placed. I had several Pmods in my design, so I added 1 second of delay to the beginning and the end of their initialization like below: int main() { init_platform(); sleep(1); RTCC_Initialize(); sleep(1); NAV_Initialize (); sleep(1); GPS_Init
  14. Hi @jpeyron I tested your ideas, but apparently none of them were able to fix this problem. I used the Pmod GPS example code with FSBL, but I do not see any GPS data on terminal. I also tested it outside, but did not make a difference. In addition, I added a couple of seconds delay at beginning of my C code, which also did not help. I should mention I had a few Pmod GPS devices, and tested all of them individually with the same code I sent you. it seems some of them are working and getting the correct GPS data after boot up with FSBL, but as soon as I try another Pmod GPS device, it
  15. Hi @jpeyron I did some follow up tests with the above configuration, but did not see any difference, though it is worth it to mention them. I commented out all of xil_printf statements and removed the inlcude xil_printf.h from the c code, hoping that printing the data to UART terminal was the problem, but it was not. I also tried to boot from SD card instead of QSPI flash memory, but even with that the problem is still there. I am almost running out of ideas and thinking maybe the FSBL is causing the issue, because every other time that FPGA is programmed via USB and there