Mahdi

Members
  • Content count

    20
  • Joined

  • Last visited

About Mahdi

  • Rank
    Member

Recent Profile Visitors

176 profile views
  1. Hi @jpeyron Awesome! I wish we had tried this earlier instead of dealing with that splitter. All 3 Pmods are working perfectly now! I really appreciate your helps. -Mahdi
  2. Hi @jpeyron I believe that is the way to go. I have occupied almost all of the GPIO pins on the Arduino header, but still the Chipkit I2C is available which I guess it is the following lines in the XDC file: ## ChipKit I2C #set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL #set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA I can easily connect my PmodRTCC to these two ports physically, but how am I supposed to communicate with it in my C code? It was easy to run the PmodRTCC example code while it was connected to ja port, but I have no idea how to talk to it when it is connected to SCL and SCA on the Chipkit. Could you please help me on this part? Thanks, Mahdi
  3. Hi @jpeyron I am not sure if you used the XDC and SDK code I gave you, but my problem right now is far beyond the c code. As soon as I hit the program FPGA button in either Vivado or SDK software, the GPS light goes on, and never turns off again, which makes me think the problem is with the bitstream. Didn't you experience such problem? The C code is the next step which we should be worried about. I am %100 sure that the attached C code is working fine, when there is only one Pmod connected to ja port in block design. Problem starts when we try to communicate with 2 pmods through one port. One thing I noticed is that all 6 pins on the top and bottom row of each J-port are electrically connected. I understand that GND and VCC could be shared, but why are the other 4 pins connected? Couldn't such connection mess up the whole splitting of the port? I am working on a project which is very close to its deadline, and the only part that is not cooperating is this port splitting. I realized that there is also a I2C port (J2) on the Arty-Z7-10 which can be used to access devices such as PmodRTCC. Do you think it is doable to connect the PmodRTCC to that port and communicate with it directly? If I do this, can I still use the PmodRTCC.h library? I am not very optimistic that we can get GPS and RTCC both working on one J-port. Thanks -Mahdi
  4. Hi @jpeyron If I connect each of the Pmods to ja port individually and not make the connections external and follow the normal procedure for making the block design (such as connecting the Pmod to ja port via sources tab of Vivado), I can see the correct output in the terminal with the same SDK code I sent you (of course you need to comment out the other Pmods code), but if I try to modify the wrapper file and XDC file manually the way you said, I can not connect to neither of the Pmods, which makes me think none of the pmods that are sharing a port could be even initialized by this method. If you look at the wrapper file, the PmodGPS and PmodRTCC pins are defined as output (which are sharing ja port) in the module, while the PmodNAV which is taking jb port in declared as inout. I thought this might cause the issue, so I changed the GPS and RTCC pins to inout, but that did not solve the problem either. I hope you can figure this out. Thanks, -Mahdi
  5. Hello again @jpeyron I guess I am still having issues with this setup. As I told you earlier, I got the bitstream generated and imported to SDK. Now, as soon as I hit the program FPGA button, the GPS led goes on and stays on forever which has no meaning to me, unless the wiring would be wrong! but I am sure that both Pmods that share the j-port are plugged in correctly. I took this outside to get a GPS lock, but did not make a difference. Neither GPS nor RTCC are working correct now, even if I just try to initialize and use one of them. My C code freezes right inside initialization of the RTCC (when I am calling RTCC_stopClock(&rtc)) which is the first Pmod I am initializing. All these are telling me we are not fully connected to these Pmods in the block design. What do you think the problem is? I have attached my block design, wrapper file, and the C code. Here is my XDC file as well. ## Pmod Header JA set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA1] set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA2] set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA3] set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA4] set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA7] set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA8] set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA9] set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA10] I did not do anything fancy. I am getting RTCC, GPS and NAV data in a loop and print them to terminal. I should also mention that this c code worked fine with when I only had GPS and NAV in my block design, and as soon as I added RTCC with your method, it stopped working. Thanks, Mahdi design_1_wrapper.v main.cc
  6. Hello @jpeyron I have already tried this, and some other pin numbers combinations such as GPS_out_pin1_io to GPS_out_pin4_io and RTCC_out_pin4_io to RTCC_out_pin4_io and vice versa. But every time I am generating the bitstream, I am getting this error which says: [DRC NSTD-1] Unspecified I/O Standard: 8 out of 154 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPS_out_pin10_io, GPS_out_pin7_io, GPS_out_pin8_io, GPS_out_pin9_io, RTCC_out_pin10_io, RTCC_out_pin7_io, RTCC_out_pin8_io, and RTCC_out_pin9_io. and [DRC UCIO-1] Unconstrained Logical Port: 8 out of 154 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPS_out_pin10_io, GPS_out_pin7_io, GPS_out_pin8_io, GPS_out_pin9_io, RTCC_out_pin10_io, RTCC_out_pin7_io, RTCC_out_pin8_io, and RTCC_out_pin9_io. this error is for the one you recommended. Apparently Vivado wants us to address all of the 8 pins of each pmod individually, and leaving them behind causes this issue. How am I supposed to fix this? Thanks, Mahdi
  7. Hello @jpeyron By following your response on this post, I have almost figured out how to modify the XDC file using the board schematics, but I have one concern. When I am looking at JA header definition in the XDC file, there are 8 lines of code as following. The first 4 lines are for the top row of pmod port, and the rest are for the bottom row. ## Pmod Header JA #set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P #set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N #set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P #set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N #set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P #set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N #set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P #set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N I am also looking at the wrapper file, and there are about 16 inout definition for the 2 pmods that I am going to use as following: inout GPS_out_pin10_io; inout GPS_out_pin1_io; inout GPS_out_pin2_io; inout GPS_out_pin3_io; inout GPS_out_pin4_io; inout GPS_out_pin7_io; inout GPS_out_pin8_io; inout GPS_out_pin9_io; inout RTCC_out_pin10_io; inout RTCC_out_pin1_io; inout RTCC_out_pin2_io; inout RTCC_out_pin3_io; inout RTCC_out_pin4_io; inout RTCC_out_pin7_io; inout RTCC_out_pin8_io; inout RTCC_out_pin9_io; I know that these pins should be called in the get_ports functions of XDC file, but how am I supposed to accommodate 16 pins names in only 8 get_ports function? Should I only use pin number 1 to 4 or 7 to 10 or something else? Thanks again, -Mahdi
  8. Thanks @jpeyron for your quick response. I really appreciate if you would help me to make the correct xdc file for this project. I have attached both the block design and wrapper file. In this block design, PmodNAV is already linked to the port jb (which I renamed to NAV_out). Now, I am trying to link PmodGPS and PmodRTCC to the top and bottom row of port ja. As you can see, the connector JA is not taken yet. The default XDC file of the Art-Z7-10 is also attached. -Mahdi Arty-Z7-10-Master.xdc design_1_wrapper.v
  9. Hi @jpeyron I believe there has been a misinterpretation. I am already aware of how to use each Pmod in Vivado. I am trying to connect 3 Pmods (NAV, GPS and RTCC) to Arty-Z7-10 board, while that board has only 2 ports available (ja, jb). I decided to split ja between GPS and RTCC using a splitter cable (since both use one row of port), and connect PmodNAV to jb. I followed your instruction above until creating the wrapper, but I guess GPS and RTCC pmods are not actually connected to the ja, and they are still external connection. When I am clicking on the Connector JA on the boards tab, it only allows me to attach one Pmod to it. I have uploaded my block design. How does Vivado realize that it should connect these 2 Pmods to ja? I generated the bitstream and it was fine, but I do not think I would be able to access the output of those 2 Pmods in SDK software. I tried to constrain the pins using XDC file, and that is where I faced my earlier question. Thanks, Mahdi
  10. Hi @jpeyron I have a follow-up question on this subject. I am trying to do the same sort of experiment with a PmodGPS and a PmodRTCC. I was able to create the wrapper and import the XDC file, but I am not sure exactly how to use it to constrain the pins for these 2 Pmods. To be clear, I can see in the XDC file that all of the lines for the Pmod ports are commented out, but should I just comment them back in or should I find out the name of the pins that are associated with the Pmods and put those pin names into get_ports functions of XDC file? Here is the JA header part of XDC file. ## Pmod Header JA #set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P #set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N #set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P #set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N #set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P #set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N #set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P #set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N How does Vivado recognize that the external connections we made for the Pmods should be connected to ja or jb? Every time I click on those external connections, it opens up about 24 pins and it is not easy to differentiate between them. I really appreciate your response. Thanks, Mahdi
  11. Mahdi

    How to split a JTAG between two pmods?

    Hi @JColvin Thanks for your quick response. This answer is exactly what I was looking for. What I meant by JTAG is the 12-pins ports that we use to connect Pmods. I guess I can make it to work now. -Mahdi
  12. Mahdi

    How to use PmodGPS without interrupts?

    Hi @jpeyron I managed to use the PmodGPS without using interrupts, and poll the data every second. My problem was that I was not using the correct type of array to store the GPS data. -Mahdi
  13. Mahdi

    How to split a JTAG between two pmods?

    Hello, I am using Arty-Z7-10 board with 3 Pmods (NAV, GPS and RTCC), while there are only 2 JTAG ports available on the board. So, I decided to buy one of these 2*6-pin JTAG splitter cables and divide one of my JTAG ports between PmodGPS and PmodRTCC (since both of them need only one row of JTAG). Now, I am trying to make a block design and connect both of them to one JTAG, but it does not seem to be feasible. When I connect the first Pmod to the JTAG port, it occupies the whole port and it does not allow me to add another Pmod to it. Is this something I have to do in Verilog, and modify my XDC file? or is there an easier way to do it by just dragging and dropping the IPs in the block design? Best, Mahdi
  14. Mahdi

    How to use PmodGPS without interrupts?

    Hello, I am using Arty board to collect GPS data every second and prints it out to terminal. To do this, I modified PmodGPS example code on github which is attached (I wrote my code in C++, rather than the original code which was in C). I wanted to completely disable interrupts and poll data every second by myself, so I removed the interrupt part of the code, but apparently PmodGPS is not working without interrupts. Even though the GPS is getting a lock, I do not see any information printed out in terminal which means GPS.ping never goes to 1. Am I doing something wrong or the GPS is not actually working without interrupts? Any help is appreciated. Best, Mahdi main.cc
  15. Hi @jpeyron, Thanks for your response. I believe I have figured out where the issue is coming from. I was initializing both of PmodNAV and PmodSD inside the main function, and that was keeping the AXI_LITE_SPI busy all the time, so I was not able to use it 2 times in a row. This is how I fixed it. I put the PmodNAV code inside a separate .cc file and defined a function in there to return navigation data as an array. I did the same thing for SD card, where it was writing anything that I was passing to its function. Then in the main file, I called the PmodNAV first, and copied its output into an array and then I called the SD card function to write the same array to the card. Apparently, After calling a function in the main code, the AXI_LITE_SPI connection that is used inside that function would be free, so you are able to use it and initialize another Pmod. But when you initialize that module directly in the main code, AXI_LITE_SPI is still connected to Micrbolaze, so you are not allowed to use it for a 2nd connection. I am all set now. -Mahdi