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About Mahdi

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  1. Hi @jpeyron I looked at the link you shared and if it is true what it says, I can only access the SD slot through SDIO controller when enabled through MIO. Does this mean that I can not control the SD card using a Verilog source code and I have to communicate with it only on PS side? My question is exactly similar to the forum you shared. I am trying to access SD slot on-board of Arty-Z7 on the PL side, rather than PS side which is normally what people do. I used the PmodSD because I did not know how to get the on-board SD slot to work and PmodSD was for testing. At the end, my purpose is to write to the SD card mounted on the on-board SD slot in the PL side, but apparently nobody has an straight answer for that. Best, Mahdi
  2. Hi @jpeyron I have been looking at the references provided and had some success communicating with a PmodSD using a modified version of the code from the MIT website. However, I am having difficulty interfacing this code with the on-board SD card slot. What is confusing is that the SD input/output ports on the ZYNQ are split when exposed through EMIO. Do you have any recommendation on how to interface with the EMIO ports directly? Thanks, Mahdi
  3. Mahdi

    All ADC channels are active on XADC demo!

    Hi @jpeyron Thanks for the suggestion. I managed to successfully use the Cora-Z7-10 project with Arty-Z7-10 board and did some tests by feeding a sinusoidal signal into different channels of ADC. Here are my observations: This project uses the buttons to select active channels of ADC, so I started with having Vp-Vn active and monitored the voltage in SDK terminal. During this test, I observed similar voltage at SDK terminal compared to input terminal, and all of single ended pins (A0-A5) were inactive, except A3 which was showing about 30 mV. This means that even though A3 was not active during this test, there was still a signal reaching to Vp-Vn pins from A3. I am not sure if this would be due to a cross-talk issue, given that A3 is not located very close to those pins. When a single ended channel was active (A0 to A5), no significant cross talk was observed which confirms that single ended channels are working properly, except A3. I also did this test for three differential channels (A6-A7, A8-A9 and A10-A11) and realized that cross talk is even higher for these channels, in a way that A8-A9 was working properly while it was active, but it was also reading about 0.3 V from Vp-Vn and 15 mV from A6-A7 and A10-A11 channels. The same scenario was true for other differential channels with smaller cross-talk values. This board should not clearly act like this, unless something is physically wrong with the channel sequencer. I hope these observations help you, whenever you have the chance to work on it. Regards, Mahdi
  4. Mahdi

    All ADC channels are active on XADC demo!

    Hi @jpeyron Thanks for your response. I am aware that in this case the two switches are only connected to two channels. My goal is to get this to work with 3 channels eventually. I did some experiments by feeding a 1 Hz, 400 mV sinusoidal signal with 0 V offset into three differential channels of Arty using a function generator and here are my observations. When both switches are high, and signal is going through 1st differential channel (V_P and V_N pins), I see the LEDs blinking with 1 Hz frequency. If I connect the signal to the 2nd (A6-A7) and 3rd (A8-A9) differential channel, I observe the same response on LEDs. If only one switch is active (SW1), then LD0 blinks no matter what channel the signal is plugged into. The same is true, when only SW0 is active. This is problematic, because I want to be able to plug in two independent differential signals at the same time. Best, Mahdi
  5. Hello, I am using the latest version of XADC demo for Arty-Z7-10. In this demo, two switches should enable two XADC channels to be read from, however all of ADC channels (A0 to A11) are active together at the same time for different switch configurations which makes me think there is cross talk between these channels or XADC demo code is broken. Have anybody experienced this? I need to have three independent active ADC channels, while I have been able to use only one of them due to this cross talk issue. Best, Mahdi
  6. Hello, I am trying to develop a simple verilog code on Arty-Z7-10 that writes to the SD card on the PL side, without having to use SDK software. To do so, I believe I need to setup my SD card pins as EMIO in the ZYNQ and modify the constraint file to uses correct pin mapping. However, I wonder if anyone has done such type of coding before and is able to provide me with more detailed information. I found this tutorial which has tried to do same thing with SPI, but it was not very detailed. I also found such SD card controller for Nexys4 board, while it seems a bit challenging to get it to work with Arty Z7 board due to different pin mappings. Any help is appreciated. Thanks, Mahdi
  7. Hello, I am working on a dual core project with mailbox IP on a Arty Z7-10 board which has been acting inconsistently. In my project, 1st core is receiving data from FPGA and sending it through mailbox to the 2nd core; the 2nd core is supposed to receive and write them to the SD card. I need to write the data at 0.5 to 1 MB/s speed, so I can not read and write fast enough on one core. As an example to show the problem, I am writing a number to the card that is being incremented by one on a loop, and plot that versus the clock cycles. Supposedly, my output should look like a straight line which it does if I do all of this on one core. Now, If I use the mailbox to send the same value between two cores, and write it on the 2nd core, I am seeing gaps and overlaps in my data which I am pretty sure is because of Mailbox. Here are two examples of what is happening. If you zoom into the time = 1.0, you can see the following gaps, and overlaps. I have set the size of mailbox at 2048, and made sure that it never fills up by checking its status on every loop. So I wonder what could be the reason for these gaps and overlaps? Can't Mailbox IP transfer data consistently between two cores? Is there any other method for doing such jobs? Thanks, Mahdi
  8. Hi @jpeyron I have good news. Since you insisted on having the delay, I went ahead and re-tested my code again. I filled up my code with delay functions and started to remove them one by one to see where it breaks, and eventually was able to figure out how much delay is needed and where it should be placed. I had several Pmods in my design, so I added 1 second of delay to the beginning and the end of their initialization like below: int main() { init_platform(); sleep(1); RTCC_Initialize(); sleep(1); NAV_Initialize (); sleep(1); GPS_Initialize (); sleep(1); .......... //call get functions here. cleanup_platform(); return 0; } It turns out that with at least 1 second of delay, GPS is functioning normally now. I had tested this with 100 ms or 500 ms delay before, but that did not work out. So, I guess a few seconds of delay seems necessary at the beginning, when we are using FSBL with Pmods. It just seems weird that some of the Arty boards do not need that delay at all, as I explained earlier. Anyway, my problem is solved, so let's just call this the final solution. Thanks again to you and your co-worker, -Mahdi
  9. Hi @jpeyron I tested your ideas, but apparently none of them were able to fix this problem. I used the Pmod GPS example code with FSBL, but I do not see any GPS data on terminal. I also tested it outside, but did not make a difference. In addition, I added a couple of seconds delay at beginning of my C code, which also did not help. I should mention I had a few Pmod GPS devices, and tested all of them individually with the same code I sent you. it seems some of them are working and getting the correct GPS data after boot up with FSBL, but as soon as I try another Pmod GPS device, it stops working. All of those GPS devices are purchased recently, so I do not know where this inconsistency issue is coming from. It seems some of them have difficulties working correctly with FSBL, but the others are fine. Have you ever had such issues before? I am assuming the PmodGPS you had is also part of the ones that have this problem, but why should it be like this? Thanks, Mahdi
  10. Hi @jpeyron I did some follow up tests with the above configuration, but did not see any difference, though it is worth it to mention them. I commented out all of xil_printf statements and removed the inlcude xil_printf.h from the c code, hoping that printing the data to UART terminal was the problem, but it was not. I also tried to boot from SD card instead of QSPI flash memory, but even with that the problem is still there. I am almost running out of ideas and thinking maybe the FSBL is causing the issue, because every other time that FPGA is programmed via USB and there is no boot up, it seems to be working. It is a very strange bug. Thanks, Mahdi
  11. Thanks @jpeyron. I am glad that it is not just me who has this problem. I hope you can find a clue. -Mahdi
  12. @D@n I am not sure what voltage you are referring to, but I am only using either USB or REG to power the board. In case of USB, I am connecting it to my laptop, and look at the terminal output in the SDK software, and in case of REG, I am using power jack port and connect it to a power supply which has a very low noise (Circuit Specialists CSI3005X5 ). Arty board has already a built-in switching regulator in it, I guess. When the board is powered via REG, USB cable is not plugged in. Also, PmodGPS is plugged into one of j-ports on the Arty, so I do not know if there is a switching noise on that power line. This issue does not seems to be due to noise on power line. I guess it has something to do with the fact that GPS library is using a UART connection, and somehow that requires the board to be plugged in via a USB cable. I know this sounds silly, but it is what it is. Thanks, Mahdi
  13. Hi @jpeyron I have read all of those tutorial about using FSBL, and I can guarantee that I am doing it correct. I verified that under several tests. If you still doubt that, you can make your own project and use my SDK code to see if there is any difference. I tried to summarize my SDK code as much as possible which is attached, but still the problem is there. As I said earlier if I program Arty via USB port, and look at the terminal, I am seeing the correct NMEA sentence format, but whenever I am uploading the code to QSPI flash memory, the only thing I see in terminal is this: GPS data = <GPS did not get a ping...> which is basically what I initialized my GPS char array with. It seems to me whenever there is a UART connection to the ZYNQ board, GPS is operating fine, but as soon as I unplug the USB from board, and power it via regulator, it stops updating my char array. Does GPS use a USB UART during its operation? I have no idea why this is happening. Thanks, Mahdi main.c
  14. Hi, I have a project that uses Arty Z7-10 with pmodgps to receive the NMEA sentences every few seconds (I am using the GPS_getSentence function directly, rather than the sample code on github). The problem I am facing is whenever I program Arty via JTAG with a USB cable, my pmodgps is working correctly, but If I program the QSPI flash memory and use FSBL to boot it up, it seems to stop working. I have other pmods that are working fine in both cases, and only gps is not working as I am expecting. This seems like a weird bug to me. Does anybody have any idea what could be wrong? Thanks, Mahdi
  15. Hi @jpeyron Awesome! I wish we had tried this earlier instead of dealing with that splitter. All 3 Pmods are working perfectly now! I really appreciate your helps. -Mahdi