cucchi

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  1. We can build a 4 lane unit for testing, The camera may be placed in a test mode where the bits are flipped to produce alternating patterns to determine "Eye Center" by adding and subtracting delays. We plan to make our board pairs on the PCB an exact length with the clocking. We should not require much delay work. Thank you
  2. Hi Zygot, Your explanations are spot on. We are taking in camera data across 16 "serdes" pairs operating @ 1.08Ghz. TThe camera is transmitting the clocking based from a clock produced from the FPGA @ 90 Mhz. The Camera is handling the workload, but the serdes is the collection system for the data. The data will be intensity checked when it arrives and placed into a buffer for analysis. Each frame will produce a subset of values that will transmitted out . So you can see only a part of the data will be kept and stored in memory, but a "ping pong" memory will be used to work the data out while another frame is collected. We will store frame output data and sream across an ethernet communication link. The data itself per pixel is 10 bit and at the most we will be storing 60000 words or 120000 bytes per frame before sample. Sample output for an entire frame is only 2400 bytes across ethernet. I appreciate your assistance.
  3. Greetings, I am trying to create a Serdes connection to a Zynq 7020 device operating at 1.08Ghz per lane with 16 lanes of data. I do not have much expertise in this area and would like some guidance on where I should look for assistance. Also I'm running a Zed Board and can attach and FMC device and if there is a 2 way communication hardware so that I can read and test the communications, that would be the best. Let me know what you think. Thank You
  4. cucchi

    Engineer

    On the DDR3 Ram some of the I/O and clocking are tuned speed dependent traces. The data I/O and Address I/O are however not shown this way in the schematics. Is the data and Address I/O supposed to have tuned traces with the clock?? Thank You
  5. cucchi

    Engineer

    Hi, Is it possible to get the board layers in Altium for Part Number 410-319 Arty board?