Davelynch

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  1. Hello everyone, I have met an issue when I use a generic counter and associate it when other component : my counter doesn't count. Firstly, I have designed three distinct function : a 2 bit counter, a multiplexer and one function allow to use 7 segment displays of Basys2. Then, I have associated these function in order to obtain one block diagram. The output of the counter are used to activate anode of 7 segment displays and they also used as input of 4 to 1 multiplexer. Finally the 4 to 1 multiplexer ptovide input for a block wich allow to light one of four 7 segement displays. When, I test only my 2 bit counter, it work correctly but when I associate this counter with other blocs diagramm, it doesn't count and stay to 0. I have tried to figure out but I haven't saw what's wrong with my design. This my vhdl code of my design : ------------------------------------------------------------------------------- -- -- Title : x7seg -- Design : Seven_Segment_Displays -- Author : Unknown -- Company : Unknown -- ------------------------------------------------------------------------------- -- -- File : C:\My_Designs\Example10\compile\x7seg.vhd -- Generated : Mon Jun 29 16:12:59 2015 -- From : C:\My_Designs\Example10\src\x7seg.bde -- By : Bde2Vhdl ver. 2.6 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity x7seg is port( clk : in STD_LOGIC; clr : in STD_LOGIC; x : in STD_LOGIC_VECTOR(15 downto 0); a_to_g : out STD_LOGIC_VECTOR(6 downto 0); an : out STD_LOGIC_VECTOR(3 downto 0) ); end x7seg; architecture x7seg of x7seg is ---- Component declarations ----- component counter_2 generic( N : INTEGER := 2 ); port ( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end component; component hex7seg_case_statement port ( x : in STD_LOGIC_VECTOR(3 downto 0); a_to_g : out STD_LOGIC_VECTOR(6 downto 0) ); end component; component mux44 port ( s : in STD_LOGIC_VECTOR(1 downto 0); x : in STD_LOGIC_VECTOR(15 downto 0); z : out STD_LOGIC_VECTOR(3 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal nq0 : STD_LOGIC; signal nq1 : STD_LOGIC; signal digit : STD_LOGIC_VECTOR (3 downto 0); signal q : STD_LOGIC_VECTOR (1 downto 0); begin ---- Component instantiations ---- U1 : counter_2 port map( clk => clr, clr => clk, q => q( 1 downto 0 ) ); nq1 <= not(q(1)); nq0 <= not(q(0)); U2 : mux44 port map( s(0) => q(0), s(1) => q(1), x => x, z => digit ); U3 : hex7seg_case_statement port map( a_to_g => a_to_g, x => digit ); an(3) <= nq0 or nq1; an(2) <= q(0) or nq1; an(0) <= q(0) or q(1); an(1) <= nq0 or q(1); end x7seg;
  2. Hello hamster. Thanks for your answer.
  3. Hi everyone ! I need some help please : when I try to implement a counter in active HDL I have this warning message : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I explain : Firstly I have designed a basic counter with Basys2 board : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity counter_2 is generic (N : integer := 4); port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end counter_2; --}} End of automatically maintained section architecture counter_2 of counter_2 is signal count: STD_LOGIC_VECTOR(N-1 downto 0); begin process(clk, clr) begin if clr = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then count <= count + 1; end if; end process; q <= count; end counter_2; Then I have produced 24-bit (q(23) downto q(0)) clock divider, my goal is to divide original frequency and obtain 2.98 Hz in using q(23) as output of the clock divider : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity clkdiv2 is port( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end clkdiv2; --}} End of automatically maintained section architecture clkdiv2 of clkdiv2 is signal q: std_logic_vector(23 downto 0); begin process(clk, clr) begin if clr = '1' then q <= X"000000"; elsif clk 'event and clk = '1' then q <= q + 1; end if; end process; clk3 <= q(23); --clk48 <= q(19); --clk190 <= q(17); -- enter your statements here -- end clkdiv2; Finally I have used block diagram of the first counter and the clock divider to light the eight LEDs of Basys 2 as binary counter : ------------------------------------------------------------------------------- -- -- Title : count8_top -- Design : Counter -- Author : Unknown -- Company : Unknown -- ------------------------------------------------------------------------------- -- -- File : c:\My_Designs\Example8\compile\count8_top.vhd -- Generated : Mon Jun 15 22:01:20 2015 -- From : c:\My_Designs\Example8\src\count8_top.bde -- By : Bde2Vhdl ver. 2.6 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity count8_top is port( clk : in STD_LOGIC; btn : in STD_LOGIC_VECTOR(3 to 3); ld : out STD_LOGIC_VECTOR(7 downto 0) ); end count8_top; architecture count8_top of count8_top is ---- Component declarations ----- component clkdiv2 port ( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end component; component counter_2 generic( N : INTEGER := 8 ); port ( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal clk3 : STD_LOGIC; begin ---- Component instantiations ---- U1 : clkdiv2 port map( clk => clk, clk3 => clk3, clr => btn(3) ); U2 : counter_2 port map( clk => clk3, clr => btn(3), q => ld( 7 downto 0 ) ); end count8_top; Finally when I implement the block diagram corresponding to the code above, I have this warning : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I don't understand what does it mean. Could you help me please?
  4. I don't really undestantd : for you what is the difference between FPGA-land compiler and software-land compiler ? But I think warning in Active HDL synthesys is like mother warning because you need just one warning then you can validate your synthesys
  5. Yes you are right JColvin : I have commented out unused pins. Thanks
  6. Finally I have found what is the problem : I have just keep pin what I need in my ucf file and I have delete rest
  7. It ' s me again for mo information this is VHDL code : library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity sw2led is port( sw : in STD_LOGIC_VECTOR(7 downto 0); ld : out STD_LOGIC_VECTOR(7 downto 0) ); end sw2led; architecture sw2led of sw2led is ---- Signal declarations used on the diagram ---- begin ---- Terminal assignment ---- -- Inputs terminals ld <= sw; -- Outputbuffer terminals end sw2led; and this the content of my ucf file : # Pin assignment for LEDs NET "ld<7>" LOC = "g1" ; NET "ld<6>" LOC = "p4" ; NET "ld<5>" LOC = "n4" ; NET "ld<4>" LOC = "n5" ; NET "ld<3>" LOC = "p6" ; NET "ld<2>" LOC = "p7" ; NET "ld<1>" LOC = "m11" ; NET "ld<0>" LOC = "m5" ; # Pin assignment for slide switches NET "sw<7>" LOC = "n3"; NET "sw<6>" LOC = "e2"; NET "sw<5>" LOC = "f3"; NET "sw<4>" LOC = "g3"; NET "sw<3>" LOC = "b4"; NET "sw<2>" LOC = "k3"; NET "sw<1>" LOC = "l3"; NET "sw<0>" LOC = "p11"; # Pin assignment for pushbutton switches NET "btn<3>" LOC = "a7"; NET "btn<2>" LOC = "m4"; NET "btn<1>" LOC = "c11"; NET "btn<0>" LOC = "g12"; # Pin assignment for 7-segment displays NET "a_to_g<6>" LOC = "l14" ; NET "a_to_g<5>" LOC = "h12" ; NET "a_to_g<4>" LOC = "n14" ; NET "a_to_g<3>" LOC = "n11" ; NET "a_to_g<2>" LOC = "p12" ; NET "a_to_g<1>" LOC = "l13" ; NET "a_to_g<0>" LOC = "m12" ; NET "dp" LOC = "n13" ; NET "an<3>" LOC = "k14"; NET "an<2>" LOC = "m13"; NET "an<1>" LOC = "j12"; NET "an<0>" LOC = "f12"; # Pin assignment for clock NET "clk" LOC = "b8";
  8. Hey every one! I use Basys2 board spartan3E 100k with Active HDL of ALDEC to study digital design. I have meet a problem when I try to implement my VHDL code the Implementation is ended and I have this message : "Warning: Implementation ended with warning(s)." In the Implementation report I have something like that : "ConstraintSystem - A target design object for the Locate constraint '<NET "an<3>" LOC = "k14";> [sw2led.ucf(37)]' could not be found and so the Locate constraint will be removed." I have tried to figure out but I don't know where the warning come from : my design is very easy , it consist just to turn on Led with slipe switch. I think the problem can come from ucf file but why? I have choose the ucf fitted to my design. Have you ever met this kind of problem? Help please!! I have attached my project if you want to see. Thanks Example1.zip