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  1. Hello everyone, I have met an issue when I use a generic counter and associate it when other component : my counter doesn't count. Firstly, I have designed three distinct function : a 2 bit counter, a multiplexer and one function allow to use 7 segment displays of Basys2. Then, I have associated these function in order to obtain one block diagram. The output of the counter are used to activate anode of 7 segment displays and they also used as input of 4 to 1 multiplexer. Finally the 4 to 1 multiplexer ptovide input for a block wich allow to light one of four 7 segement displays. When, I test
  2. Hello hamster. Thanks for your answer.
  3. Hi everyone ! I need some help please : when I try to implement a counter in active HDL I have this warning message : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I explain : Firstly I have designed a basic counter with Basys2 board : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity counter_2 is generic (N : integer := 4); port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end counter_2; --}} End of au
  4. I don't really undestantd : for you what is the difference between FPGA-land compiler and software-land compiler ? But I think warning in Active HDL synthesys is like mother warning because you need just one warning then you can validate your synthesys
  5. Yes you are right JColvin : I have commented out unused pins. Thanks
  6. Finally I have found what is the problem : I have just keep pin what I need in my ucf file and I have delete rest
  7. It ' s me again for mo information this is VHDL code : library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity sw2led is port( sw : in STD_LOGIC_VECTOR(7 downto 0); ld : out STD_LOGIC_VECTOR(7 downto 0) ); end sw2led; architecture sw2led of sw2led is ---- Signal declarations used on the diagram ---- begin ---- Terminal assignment ---- -- Inputs terminals ld <= sw; -- Outputbuffer terminals end sw2led; and this the content of my ucf file : # Pin assignment for
  8. Hey every one! I use Basys2 board spartan3E 100k with Active HDL of ALDEC to study digital design. I have meet a problem when I try to implement my VHDL code the Implementation is ended and I have this message : "Warning: Implementation ended with warning(s)." In the Implementation report I have something like that : "ConstraintSystem - A target design object for the Locate constraint '<NET "an<3>" LOC = "k14";> [sw2led.ucf(37)]' could not be found and so the Locate constraint will be removed." I have tried to figure out but I don't know where the warning come from :