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  1. Just got new green PCBs for line out board. So much better than prototype..
  2. Moving forward.. 4096 (12 bit) LUT with 32bit sine values played via 32bit DAC at 48kHz gives this. Not perfect but I'm getting there.. I've used this boad for testing https://www.ebay.com/itm/ES9028Q2M-ES9028-I2S-input-decoder-board-mill-board-DAC-balanced-output/132317494575?hash=item1ecebcbd2f:g:4VcAAOSwOuRZrMaq The goal is to get THD+N below 0,001%. It seems I might need to learn FIR filtering for that.
  3. Good day everyone, just a quick update. Everything is going quite slow but fine with this project. Unfortunately I can only spare up to 1-2 hours a day for it, but have learned a lot already. So far I've managed to: Design the DAC pcb and generate all clocks for it (16 bit, 48kHz); Build quite stable square, triangle and sine (1000 sample LUT) generators; Make small internal audio switcher (dependant on hardware switch position); Achieve ~0.2% THD+N on the differential (DRV134) output with 1kHz @ ~4Vpp; Next step is to wait for revisioned and better quality P
  4. @hamster that is impressive list of projects You have done. Also few related to audio - Its going to be quite a nice read for me about spdif and Analog Wing. STGL5000 example is nice, however I doesn't seem to face and solve same (clocking) problems as I have.. Thanks anyway!
  5. Well, i meant OOP in away that You have a definition of the object and then have to instantiate it (even several times if need be). The GUI way is quite ok, once You figure out that it still has to be generated and set as top, later its much easier to understand what is going on with the desing. Yesterday I've figured that I can use external editor (Sublime) and that was great performance enhancement for me. It took some time to realise that for this purpose I need PISO shifter and after whole day today I've got clocks and that shifter working. sys_clock = 100MHZ, mclock = 12.2
  6. @xc6lx45 thanks for picturesque code snippet. That actually opened my eyes - verilog is OOP and all blocks has to be instantiated. So I've managed to hack this together: and even write test bench with 100MHz sysclock, so I could simulate the whole thing. Most of the thing seems to be working, except the output serializer.. Just cant make it work.. I was looking at @bikerglen i2s example for couple hours, but I just cant figure it out, even if I throw everything input related out. Somehow I'm not completely sure how it works. Any suggestions where to look/read or m
  7. I still dont get the basic parts of design.. if I have something like this It seems that RTL is still looking for hardware ports by the name of its output - it ignores if I have those nice ports created.. why is it so? or am I missing something? It this case I could just delete these ports and it wouldn't care. Same with the clock.. If i start clocking wizard, setup desired freq and then rightclick that block and use this wiring wizard it connects those two ports (reset and sys_clock). But how does it know where to get the clock as my constraints file is commented out.
  8. @xc6lx45 thanks for Your detailed answer. It makes a lot of sense and it should not be too hard for me to do it. Also a bit distorted sine is ok for now (maybe I'll get back to it later) just to make sure it uses the whole dynamic range for (in my case 24bits).
  9. I'm trying to construct different signal generators.. so I could play some data to my breadboarded dac. The idea is to have a tick generator at, say 1kHz frequency and then different sort of samplers to play samples. https://gist.github.com/ignazas/dc15fb4afd7e0204825baa359cd17bbb This is what i have hacked together to get sinus and I also thoughts regarding sawtooth - this one could be generated as a simple counter but i dont know how to control the frequency.. Even if I have a predefined step(resolution), say (full scale)/256, i will get signal frequency 256 times slower
  10. Oh dear.. what a dumb mistake. Now I see it.. thanks @xc6lx45!
  11. thanks for the comment, ive tried that now.. ##Pmod Header JA set_property -dict { PACKAGE_PIN G13 } [get_ports { sdata }]; set_property -dict { IOSTANDARD LVCMOS33 } [get_ports { sdata }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 } [get_ports { sclock }]; set_property -dict { IOSTANDARD LVCMOS33 } [get_ports { sclock }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 } [get_ports { mlck }]; set_property -dict { IOSTANDARD LVCMOS33 } [get_ports { mlck }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 } [get_ports { lrck }]; set_property -dict {
  12. Good day everyone, so I'm trying out @bikerglen i2s IP, but facing some general Vivado error even before that.. My current setup (Arty-7): But when generating bitstream im getting: I was trying to google that one, but unfortunately its not clear why Vivado does not recognize my default declarations in .xdc file.. any ideas?
  13. @bikerglen thanks for Your comment - I will definitely try Your I2S code. For me its still quite hard to understand the whole architecture and design patterns of FPGA programming. I still have to read a lot and many videos to watch before I even try it. But lets see how fast I can get it:)) I see You have some experience with audio, maybe You have an idea how to calculate I2S delay on FPGA? If its 48k 24bit signal then it takes 1/48000 = 0.00002083333 s for every bit to arrive 0.00002083333 * 24 = 0.0005 s for every 24 bits and that is only deserialization, same for seria
  14. Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]),