ATIF JAVED

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  1. ATIF JAVED

    JTAG HS3 not detected by Vivado

    Try these posts may be it helpful for you https://forum.digilentinc.com/topic/13275-xup-usb-jtag-programmer/#comment-40008 https://forum.digilentinc.com/topic/16584-hardware-manager-recognize-problem/#comment-40307 Best, ATIF JAVED
  2. ATIF JAVED

    Implementation Problem in vivado 2017.4

    Hello all of you hope you are in a good health I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3] to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved Any kind of help in this regard is appreciable . Best, ATIF JAVED
  3. ATIF JAVED

    Hardware manager recognize problem

    Thank you very much problem is resolved
  4. ATIF JAVED

    Hardware manager recognize problem

    Hello All of you I am trying to debug my code on picozed board . Board is successfully recognized in my college desktop PC but when i tried to connect it in my pc(vivado 2017.4 window 10) hardware manager . It give me error that no hardware is open . I use diligent JTAG-USB programming cable for debugging . I recheck drivers and found out that cable is also identified by PC. Please give me a suggestion what should i do. Below you can find the screenshots of device manager for driver installation and hardware manager status.
  5. ATIF JAVED

    Fir compiler core as a decimation

    Sir fir decimator gives output after complete implementation of (filter->down sample) it does give me the independent output of filter so i cannot remove this transient response by myself one of the implementation is that i only use fir compiler for filter not for decimator and then down-sample it by myself using my own logic but i cannot satisfy with this type of implementation because if fir compiler give us a feature of decimator then why not we use it efficiently
  6. ATIF JAVED

    Convert FPGA active low logic to active high

    Hello, I am using xilinx spartan 6 sp6-x9 board in which its led's and switch works on active low logic. Is it possible to convert switch and leds to to active high logic
  7. ATIF JAVED

    ADC DAC SELECTION

    I want to interface DAC and ADC with some fpga evaluation board My requirement of ADC and DAC is following DAC input ->sampling_rate=2MS/s frequency=455khz ADC Input ->Signal bandwidth=400khz i have no problem of resolution So someone please guide me or refer me some models of adc and dac along with some FPGA evaluation board that complete my requirements . Also refer me if anyone know about some board that have build in adc dac along with FPGA Any kind of help in this regard would be much appreciable
  8. ATIF JAVED

    Fir compiler core as a decimation

    Filtering a signal introduces a delay. This means that the output signal is shifted in time with respect to the input. For example my input is [1 2 3 4 5 6 7 8 9 10] decimation factor is 2 filter type is fir first i apply to a filter to input and filtered output is for example 0.0001 0.0003 0.1 0.15 0.17 0.16 0.18 0.16 0.17 0.15 I need to discard first two values that is a transient response(group delay) after discarding i have these values 0.1 0.15 0.17 0.16 0.18 0.16 0.17 0.15 now i pad some values at the end to make the vector length equal 0.1 0.15 0.17 0.16 0.18 0.16 0.17 0.15 0.15 0.15 finaly down sample it by factor of 2 0.1 0.17 0.18 0.16 0.15 fir compiler doesn't give option to handle this transient response which is known group delay of a filter so how i manage this problem in verilog Below you can find a matlab code that explain the complete scenario following flow is follow in the below code bits->interpolation->decimation->bits detail flow bits->upsample->interpolation filter->decimation_filter->downsample->bits you can find its explanation from this link as well https://www.mathworks.com/help/signal/ug/compensate-for-delay-and-distortion-introduced-by-filters.html clc; clear all; close all; idata=ones(1,100); nfilt=30; factor = 10; alpha = 0.5; idata = randi([0 1],100,1); //bits that becomes the input of upsample //****************** below code represent the interpolation implementation in which first we upsample the code and then filter it and finaly discard transient response xr = upsample(idata,factor); h1 = intfilt(factor,2,alpha); y = filter(h1,1,xr); delay_int = mean(grpdelay(h1)); y(1:delay_int) = []; //******************* ///**pad some values at the end of data so that my vector length is eqa y=[y;repelem(y(end),delay_int)']; //**decimation fir filter which [B,A]=fir1(30,1/factor); dec_filter=filter(B,A,y); delay_dec = mean(grpdelay(B)); dec_filter(1:delay_dec) = []; //** discard the transient responese of a filter at a start ///**pad some values at the end of data so that my vector length is equal dec_filter=[dec_filter;repelem(y(end),delay_dec)']; ///** finaly down sample it to complete decimation dec=downsample(dec_filter,factor); deb=round(dec); bits=de2bi(deb,'left-msb'); [er,bit]=biterr(idata,bits);
  9. ATIF JAVED

    Fir compiler core as a decimation

    I am trying to implement Decimation on FPGA and Matlab For this task i chose following design parameters Filter type=window hamming hamming method filter order=30 decimation factor=10 input sample rate=2Ms/s output sample rate=200ks/s Normalized cuttof =1/decimation factor First i implement it on MATLAB and use this sequence Filter handle filter delay downsample Using above sequence i successfuly implement it on MATLAB For FPGA i use fir compiler core in which i paste the same coefficients that is generated through matlab But the problem i face is fir compiler core directly gives you the decimated output without handling fitler delay so what should i do if want to handle this filter delay in xilinx Fir compiler core sequence Filter-downsample