dgottesm

Members
  • Content Count

    31
  • Joined

  • Last visited

About dgottesm

  • Rank
    Frequent Visitor

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. dgottesm

    Odd timing violation

    Hi @[email protected]! actually, it’s technically not a FIFO, because the it doesn’t send the first out, but 5 other bytes in memory, not in order they were received... I have an algorithm telling me which addresses to read...
  2. dgottesm

    Odd timing violation

    @xc6lx45 Actually, I see the problem. I made a serious error in the routing on my part. But I still want to hear any insight you have about my design and dealing with multiple clocks...
  3. dgottesm

    Odd timing violation

    @xc6lx45 Indeed, there are two clocks in the design. I have simulated the entire design, with a full testbench with full success, so I hope that it doesn't have serious issues. I thought out the design long and hard, so in theory it should work, but I have never synthesized a complicated design before. Basically, I have a dual port RAM, and data is being read at a different clock then the write. In the BRAM controller, there are two systems of clocks, one for the read (lets say 250 MHz), one for the write (lets say 25 MHz), but there is some overlap in the systems. The data is
  4. dgottesm

    Odd timing violation

    @xc6lx45 So what should I do?
  5. @xc6lx45 Thanks, I did not notice that set of options. However, it is an external clock, and I am inputting it in a clock capable pin... should/can I still choose global buffer?
  6. dgottesm

    Odd timing violation

    I am working on the failed timing report of my design, and so far I am doing good, setting most of the violations as false paths (I know, user beware). I have reached the last two errors and I don't really know what to do. I have a BRAM in my design, and I have a single register controlling the write_en, and Vivado tells me I have a timing violation and I don't know how to fix it or what the problem is (Ignore the first error in the pictures... I have an idea of how to fix... might be a multicycle) I suppose that clue #1 is that Vivado lists the violation as an inter-clock path, so I guess
  7. Hi When inputting an external clock into the clock wizard, does the input have to be driven by a BUFG, or can it be driven by a simple IBUF Meaning, is this ok?
  8. @[email protected] thanks for the tip on instantiating a BUFG yes, I need the halved clock for the design/logic as well. But I suppose I can half the clock locally in the module using an enable bit... it just means that I have to add that in my design. I already designed to receive a half clock...
  9. @[email protected] thanks for your answer. Can you please tell me in a straightforward way how to route an input to a BUFG? I have heard of it, but I can’t find someone saying how. What does an OBUF do and how does it half the clock rate? I have heard that it is unwise to half a clock logically ie with a flip flop. i don’t specifically want a PLL, an MMCM is fine if it gets the job done. I have never instantiated a PLL (or any primitive for that matter). I have only used the Vivado wizards.
  10. Hi I am inputting an external clock into my Basys3. I want to input the clock into a clock wizard and the output of the clock wizard would be a clock of the same frequency, and a clock of half the frequency, so hypothetically, not a tall order. The problem is that the data sheet of the clock (and the data coming with it) says the frequency of the clock is 28.63636 MHz, +- 50 ppm. So, I typed into the clock wizard the exact frequency for the input and the two outputs, and when I tried to implement, it failed and I got the following message: [DRC 23-20] Rule violation (PDRC-43) PLL_ad
  11. dgottesm

    VGA, YPbPr, Basys3

    @jpeyron Aye, there’s the rub. Sync on Y/green requires another 300 mv. I asked the question as well on stackexchange. https://electronics.stackexchange.com/questions/376891/ypbpr-vga-basys3 there is an interesting idea there about level shifting the Y and adding a switch.. I ordered the appropriate cable... I will write a basic video generator... We will see what happens
  12. dgottesm

    Sync on green VGA

    General question: Has anyone here ever managed to do a VGA project with 'sync on green' to drive component video? Looking for the most basic implementation, looking for a stable picture, not quality
  13. dgottesm

    VGA, YPbPr, Basys3

    The Basys3 manual says that the VGA analog outputs can drive between 0 and 0.7 volts. Does anyone know if, from a purely analog perspective, this can drive “component video”, or video in YPbPr, by using the outputs normally used for RGB for YPbPr? Obviously I would have to play with the Y to implement “sync on Y” In the end, I would connect a simple VGA to component cable and connect to s component screen
  14. Hi I am back to working with customizing the rgb2dvi IP. As mentioned in an earlier post, I made the changes in .vhd files, and I set the compile order of the .xdc files. I wrote a simple video generator (which also outputs the appropriate timing signals to the IP) in verilog, and a 'top' module that connects the two together. The design needs an external clock, which I will supply and I found which pin I need to use to get a universal clock. I have two questions: 1) The IP as a asynchronous reset, and the documentation says 'Asynchronous reset of configurable polarity. Assert,
  15. Hi @BogdanVanca Thanks very much for your answer. For my first question, I understand that all I need to do is 1) set kClkPrimitive : string :="MMCM" and 2) set kClkRange: natural:=5;. Is that true? For my second question, I did not understand your answer: What do I do with the 2 xdc files from the IP? Do I add them to my board xdc file? Where do set the clk to 27 MHz? (I am taking the clock from an external source)