dgottesm

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  1. dgottesm

    Odd timing violation

    Hi @D@n! actually, it’s technically not a FIFO, because the it doesn’t send the first out, but 5 other bytes in memory, not in order they were received... I have an algorithm telling me which addresses to read...
  2. dgottesm

    Odd timing violation

    @xc6lx45 Actually, I see the problem. I made a serious error in the routing on my part. But I still want to hear any insight you have about my design and dealing with multiple clocks...
  3. dgottesm

    Odd timing violation

    @xc6lx45 Indeed, there are two clocks in the design. I have simulated the entire design, with a full testbench with full success, so I hope that it doesn't have serious issues. I thought out the design long and hard, so in theory it should work, but I have never synthesized a complicated design before. Basically, I have a dual port RAM, and data is being read at a different clock then the write. In the BRAM controller, there are two systems of clocks, one for the read (lets say 250 MHz), one for the write (lets say 25 MHz), but there is some overlap in the systems. The data is being written at 25 MHz, and there is an target address register (which is synchronous to the 250 MHz clock) sitting at 0. When the distance between the target address register and the write address register is a certain amount, the read address (also synchronous to the 250 MHz clock) reads 5 values, and the target address advances one, closing the distance by one, until the next byte is written, and it continues, until a certain amount of data has been processed, and the whole thing starts again So there is some dependency. At first, all the paths with violations were because of the reset values after 'a certain amount of data had been written'. I decided that those values would definitively get reset because of the design, so I wasn't so worried, but I did learn that such dependencies made a difference. Now I am dealing with a dual port ram, with two clocks, and I have this violation. If you want to see the BRAM controller module, I can send it to you privately, and you can tell me if you think it is a serious problem (I am a student, and my adviser isn't much help) Thanks
  4. dgottesm

    Odd timing violation

    @xc6lx45 So what should I do?
  5. dgottesm

    Input clock of clock wizard

    @xc6lx45 Thanks, I did not notice that set of options. However, it is an external clock, and I am inputting it in a clock capable pin... should/can I still choose global buffer?
  6. dgottesm

    Odd timing violation

    I am working on the failed timing report of my design, and so far I am doing good, setting most of the violations as false paths (I know, user beware). I have reached the last two errors and I don't really know what to do. I have a BRAM in my design, and I have a single register controlling the write_en, and Vivado tells me I have a timing violation and I don't know how to fix it or what the problem is (Ignore the first error in the pictures... I have an idea of how to fix... might be a multicycle) I suppose that clue #1 is that Vivado lists the violation as an inter-clock path, so I guess that means that the clock of source register of the design, which I know what it is, is not the same as the clock of the BRAM itself, which I don't know. I also see that most of the slack is because of net delay. What can I do to fix this? Thanks
  7. dgottesm

    Input clock of clock wizard

    Hi When inputting an external clock into the clock wizard, does the input have to be driven by a BUFG, or can it be driven by a simple IBUF Meaning, is this ok?
  8. dgottesm

    Extremely exact clock frequency

    @D@n thanks for the tip on instantiating a BUFG yes, I need the halved clock for the design/logic as well. But I suppose I can half the clock locally in the module using an enable bit... it just means that I have to add that in my design. I already designed to receive a half clock...
  9. dgottesm

    Extremely exact clock frequency

    @D@n thanks for your answer. Can you please tell me in a straightforward way how to route an input to a BUFG? I have heard of it, but I can’t find someone saying how. What does an OBUF do and how does it half the clock rate? I have heard that it is unwise to half a clock logically ie with a flip flop. i don’t specifically want a PLL, an MMCM is fine if it gets the job done. I have never instantiated a PLL (or any primitive for that matter). I have only used the Vivado wizards.
  10. dgottesm

    Extremely exact clock frequency

    Hi I am inputting an external clock into my Basys3. I want to input the clock into a clock wizard and the output of the clock wizard would be a clock of the same frequency, and a clock of half the frequency, so hypothetically, not a tall order. The problem is that the data sheet of the clock (and the data coming with it) says the frequency of the clock is 28.63636 MHz, +- 50 ppm. So, I typed into the clock wizard the exact frequency for the input and the two outputs, and when I tried to implement, it failed and I got the following message: [DRC 23-20] Rule violation (PDRC-43) PLL_adv_ClkFrequency_div_no_dclk - The computed value 755.980 MHz (CLKIN1_PERIOD, net clk_54_in_clk_wiz_2) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X0Y2 (cell clk_wiz_2/inst/plle2_adv_inst) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (18.518997), multiplication factor CLKFBOUT_MULT_F (14) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device. So what should I do? I know that it is a PLL, so hypothetically, I can give it an easier frequency that is close enough to the actual frequency and let the PLL lock on to the actual frequency. Any comments or suggestions?
  11. dgottesm

    VGA, YPbPr, Basys3

    @jpeyron Aye, there’s the rub. Sync on Y/green requires another 300 mv. I asked the question as well on stackexchange. https://electronics.stackexchange.com/questions/376891/ypbpr-vga-basys3 there is an interesting idea there about level shifting the Y and adding a switch.. I ordered the appropriate cable... I will write a basic video generator... We will see what happens
  12. dgottesm

    Sync on green VGA

    General question: Has anyone here ever managed to do a VGA project with 'sync on green' to drive component video? Looking for the most basic implementation, looking for a stable picture, not quality
  13. dgottesm

    VGA, YPbPr, Basys3

    The Basys3 manual says that the VGA analog outputs can drive between 0 and 0.7 volts. Does anyone know if, from a purely analog perspective, this can drive “component video”, or video in YPbPr, by using the outputs normally used for RGB for YPbPr? Obviously I would have to play with the Y to implement “sync on Y” In the end, I would connect a simple VGA to component cable and connect to s component screen
  14. dgottesm

    reset signal in rgb2dvi IP

    Hi I am back to working with customizing the rgb2dvi IP. As mentioned in an earlier post, I made the changes in .vhd files, and I set the compile order of the .xdc files. I wrote a simple video generator (which also outputs the appropriate timing signals to the IP) in verilog, and a 'top' module that connects the two together. The design needs an external clock, which I will supply and I found which pin I need to use to get a universal clock. I have two questions: 1) The IP as a asynchronous reset, and the documentation says 'Asynchronous reset of configurable polarity. Assert, if PixelClk and SerialClk are not within spec.'. The comment next to the source code itself says 'asynchronous reset; must be reset when RefClk is not within spec'. Can someone explain exactly what this means in simple English? I could not find any signal called 'RefClk' in the design. Practically, what should I do with the reset? 2) I attached a picture of the synthesis schematic from Vivado. Now, my video generator has a video data output of 24 bits (3 8 bit RGB values), and the IP has a video data input of 24 bits. So what are the D and Q signals coming out of the video generator, and why are they 2 bits each?
  15. dgottesm

    rgb2dvi IP customization Part 2

    Hi @BogdanVanca Thanks very much for your answer. For my first question, I understand that all I need to do is 1) set kClkPrimitive : string :="MMCM" and 2) set kClkRange: natural:=5;. Is that true? For my second question, I did not understand your answer: What do I do with the 2 xdc files from the IP? Do I add them to my board xdc file? Where do set the clk to 27 MHz? (I am taking the clock from an external source)