subasheee

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  1. Hi @jpeyron Thanks for your reply. Apparently, the s_axi_aresetn pin of AXIuartlite should be made logic high after few nano seconds. Initially i kept it at high from starting of simulation. Regards, Subash
  2. Hi, I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP. The AXI Uartlite is configured as follows. CLK 1MHz, baud rate 9600, data bits 8 S_AXI_wvalid <= '1'; S_AXI_wstrb <= '1'; S_AXI_awvalid <= '1'; S_AXI_aresetn <= '1'; S_AXI_awaddr <= "0100"; S_AXI_wdata <= "00000000000000000000000001010011"; When I simulate, the TX port output of AXI Uartlite just remains ‘X’ state instead toggling as per S_AXI_wdata. I have simulated upto 4 seconds and ll the values are initialized from the beginning of simulation. Am I missing any configuration setting? or anything needs to be carried out to get teh data at TX port ? Help is much appreciated. Regards, Subash
  3. HI @D@n Thanks for the reply. After few simulations, i figured out that the frequency of Tvalid should be same as input signal sample rate (as you have suggested) and the pulse width of Tvalid should be same as the width of clock pulses to the FFT IP-core. For eg: FFT clock at 1MHz, input signal at 10kHz, Tvalid should be clocked at 10kHz at 1% duty (ON for 1us and OFF for 0.1ms-1us) Regards, Subash
  4. Hi @D@n, I tried clocking the s_axis_data_tvalid of FFT IPcore at the same frequency as that of the sampling frequency of input signal. The frequency resolution does changes but not as that of the input signal. I simulated two scenarios 1. DDS complier generates 61Hz sine signal at a sample rate of 1MHz, it is down sampled to 10kHz then given as input to the FFT IP core clocked at 1MHz. FFT buffer=16384. In this case, Actual frequency resolution(supposed to be)=10kHz/16384, Frequency resolution with FFT IPcore clocked at 1MHz=1Mhz/16384 Frequency resolution with FFT IPcore clocked at 1MHz and Tvalid clocked at 10kHz=500kHz/16384 2. DDS complier generates 61Hz sine signal at a sample rate of 1MHz, it is down sampled to 10kHz then given as input to the FFT IP core clocked at 100kHz. FFT buffer=16384. In this case, Actual frequency resolution(supposed to be)=10kHz/16384, Frequency resolution with FFT IPcore clocked at 100kHz=100khz/16384 Frequency resolution with FFT IPcore clocked at 100kHz and Tvalid clocked at 10kHz=50kHz/16384 So, I am not able to figure out, why the sampling frequency of FFT IP core is half of the clock frequency, if the Tvalid is clocked at the sample rate of input signal to the FFT IP core. I have attached the simulation results for your reference. The details of the signals are as follows INP_CLK -->Clock input to the FFT IP core, 100kHz ACT_SINE -->Input signal to FFT IP core sample at 10kHz SQUARE_OUT-->FFT output-magnitude axis TUSER_delay -->FFT output-frequency axis TVALID -->FFT output valid signal Regards, Subash
  5. Dear @D@n Yes, you are correct. But, FFT has only single clock. If i make the clock frequency of FFT as the sampling frequency of input signal then then the FFT computation time increases significantly for low sample rate input signal (eg: 5kSps). Unlike FIFO blocks, FFT does not have two separate clocks for input and output, so that i have flexibility to read, process and write at different clock frequencies. Is there any solution to just read the signal at lower sample rate but carry out FFT processing and writing at high clock frequencies ? Regards, Subash
  6. Hi, I am am able to compute the FFT using IP core block available in Vivado 2017. However, whatever is the sample rate of input signal to FFT IPcore, the frequency resolution of the FFT is fixed by clock frequency of the FFT. Example Frequency resolution = sampling frequency/number of samples DDS compiler generates sinusoidal frequency 976.56Hz at a clock freq of 1MHz,therefore the sample rate is 1Ms/s. this signal is given as input to the FFT IPcore 9.0 which is clocked at 5MHz with number of samples as 65536. therefore, Expected frequency resolution = 1MHz/65536, however, measured frequency resolution =5MHz/65536 in Behavioral simulation (Vivado 2017) It does not matter what is the clock frequency of DDS compiler, the frequency resolution of the FFT remains at 5MHz/65536. But, in reality the frequency resolution is fixed by sample rate of input signals and the buffer size of FFT. So, my question is, why in FPGA the frequency resolution is fixed by the clock frequency of FFT rather than sample rate of the input signal. Help is much appreciated. Regards, Subash
  7. Dear @D@n Sorry for the late reply; thanks for your responses. Your suggestions are helpful. i considered your suggestions 1 and 2 for square root, i simply delayed the m_axis_data_tuser by 33 samples using the same square root block. Regards, Subash
  8. Hi @D@n Thanks for your reply, I understood the difference between pipeline and burst modes. I figured out the reason for 33 samples delay between m_axis_data_tuser and m_axis_data_tdata. I used multiplier, adder and square root calculator to compute the magnitude of FFT which is sqrt(Re^2+Imag^2). The adder and multiplier took 2 clock cycle and the square root block (CORDIC) took 31 clock cycles. So, the output of m_axis_data_tdata is 33 clock cycles behind the m_axis_data_tuser. Do you have any better suggestions to calculate the magnitude of FFT which is sqrt(Re^2+Imag^2) without introducing the delay ? Of course i can overclock the multiplier, adder and square root block to reduce the latency, but other than that is there any better solution ? Regards, Subash
  9. Hi @D@n Hi D@n, Thanks for your inputs, my responses are as follows. Do let me know, if i am not clear or has to provide further details. 1. I often counsel folks not to use burst mode, such as you are using, but the pipeline mode instead. This is due to the added logic and complexity of properly setting up the valid and ready wires on the input. Please see the attached image file of the design file. s_axis_data_tvalid is always set to 1. I am not concerned with the data loss during FFT computation 2. You never told me the sample rate (or clock rate even) of the FFT. Are you running it at 1MHz? or 100MHz? (Best performance would be at 100MHz or so ...) The FFT clock is same as the sampling frequency 100kHz or 50kHz. Basically, I did Behavioral simulation in Vivado 2017.4 3. Look at the FFT manual--there's a flag that's used to note the first valid value from the FFT (and the last IIRC). You'll need to synch to that value, or you'll have these offset problems you noted above. You mean to say m_axis_data_tvalid and m_axis_data_tlast?. If so, I am synchronizing with these two flags. Please see the attached figure named “signals”. You can also see the TUSER ie XK_index in the figure names “signals1”. For this Behavioral simulation, the specifications are DDS sine frequency 97.65, DDS clock=100kHz, FFT clock=100kHz and FFT size=16384 4. If you have samples coming in at 1MHz, but you want frequency resolution between 0-10 kHz, then you'll want to filter and downsample the FFT by a factor of (1MHz/20 kHz=) 50. Yes I do agree with your comment, I did down sampling and carried out FFT. DDS compiler generated 48.8Hz sinusoidal signal with 1MS/s, it is down sampled to 10kS/s and given as input to FFT IP core. The clock signal of FFT IP core is 1MHz. I though the clock frequency of FFT fixes the sampling frequency, But I was wrong. Apparently FFT clock is nothing to do with the sampling frequency of the signal. Sampling frequency is decided by sample time of the input signal to the FFT block. So altogether, the unresolved issue is the offset 33 samples in the XK_index. I am synchronizing with m_axis_data_tvalid and m_axis_data_tlast. SDo I need to sync with other signal ? Regards, Subash
  10. Hi @D@n I went through the link provide by @jpeyron for FFT which is informative. I was able to perform FFT on the synthesized sine signals using DDS compiler. I tried FFT for various frequencies of sine signals and their details are as follows. FFT implementation: Radix-2 burst I/O, Natural order, 16384, 1 channel, Fixed-point, scaled, truncation, Use 3-multiplier structure, Use CLB-logic Sine signal 1: sampling frequency: 100kHz, Signal frequency: 48.828Hz, FIFO size:16384, Transform length: 16384, Frequency resolution: 100kHz/16384 Calculated BIN index for peak value= 48.828Hz/(100kHz/16384) = 8 , XK_index for peak = 41 Sine signal 2: sampling frequency: 50kHz, Signal frequency: 48.828Hz, FIFO size:16384, Transform length: 16384, Frequency resolution: 50kHz/16384 Calculated BIN index for peak value= 48.828Hz/(50kHz/16384) = 16 , XK_index for peak = 49 DC signal: sampling frequency: 50kHz, Signal frequency: 0.7Hz, FIFO size:16384, Transform length: 16384, Frequency resolution: 50kHz/16384 Calculated BIN index for peak value= 48.828Hz/(50kHz/16384) = 0.23 ~ 0, XK_index for peak = 33 If you observe, even for DC signal (0.7Hz) the FFT bin provided by XK_index is 33 bins, if you subtract this offset for each signal then the Calculated BIN index for peak value matches with the peak value in FFT Signal 1: XK_index for peak = 41, XK_index for peak (DC) = 33, 41-33 = 8 Signal 2: XK_index for peak = 49, XK_index for peak (DC) = 33, 49-33 = 16 Signal 3: XK_index for peak = 33, XK_index for peak (DC) = 33, 33-33 = 0 So, my questions are 1. why there is a offset in XK_index values? am i missing some configuration setting ? 2. Can i buffer the signals to FIFO at low frequency (10kHz), unbuffer at high frequency 1MHz and carry out FFT ?. In this way i can reduce the FFT computation time without compromising frequency resolution. But, as the FFT block samples the signal at 1MHz, that means FFT block take the sampling frequency as 1MHZ ? Help is much appreciated. Regards, Subash
  11. Hi @jpeyron Thanks for your the link. I learned certain details about FFT and able to compute FFT using FFT IPcore V9.0. Regards, Subash
  12. Hi, I am trying to compute FFT of a synthesized square wave of frequency 100Hz. The 100Hz signal has to be sampled at 1kHz. So, I kept the clock frequency of FIFO, FFT_IPcore and other blocks at 1ms. I have attached the screenshot of the design file and simulation results. From the simulation output, it can be observed that the buffer stores for 512 samples and the un-buffer after 512*1ms. But, there is no output from the FFT block. I would like to know whether my approach is correct or I am committing any mistake in the way the blocks have to be integrated. Help much appreciated. Regards, Subash
  13. Hi JColvin, Thanks, you are correct. Apparently the unused ADC pins should not be kept open. Th unused pins should be either grounded or connected to a external buffer circuits. If not somehow, the siganl given in one ADC pins is passed to other pins. Regards, Subash
  14. Hi JColvin, Yes i do. I connected all the N-pins to GND in the Pmod connector.