subasheee

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  1. Hi @jpeyron Thanks for your reply. Apparently, the s_axi_aresetn pin of AXIuartlite should be made logic high after few nano seconds. Initially i kept it at high from starting of simulation. Regards, Subash
  2. Hi, I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP. The AXI Uartlite is configured as follows. CLK 1MHz, baud rate 9600, data bits 8 S_AXI_wvalid <= '1'; S_AXI_wstrb <= '1'; S_AXI_awvalid <= '1'; S_AXI_aresetn <= '1'; S_AXI_awaddr <= "0100"; S_AXI_wdata <= "00000000000000000000000001010011"; When I simulate, the TX port output of AXI Uartlite just remains ‘X’
  3. HI @[email protected] Thanks for the reply. After few simulations, i figured out that the frequency of Tvalid should be same as input signal sample rate (as you have suggested) and the pulse width of Tvalid should be same as the width of clock pulses to the FFT IP-core. For eg: FFT clock at 1MHz, input signal at 10kHz, Tvalid should be clocked at 10kHz at 1% duty (ON for 1us and OFF for 0.1ms-1us) Regards, Subash
  4. Hi @[email protected], I tried clocking the s_axis_data_tvalid of FFT IPcore at the same frequency as that of the sampling frequency of input signal. The frequency resolution does changes but not as that of the input signal. I simulated two scenarios 1. DDS complier generates 61Hz sine signal at a sample rate of 1MHz, it is down sampled to 10kHz then given as input to the FFT IP core clocked at 1MHz. FFT buffer=16384. In this case, Actual frequency resolution(supposed to be)=10kHz/16384, Frequency resolution with FFT IPcore clocked at 1MHz=1Mhz/16384
  5. Dear @[email protected] Yes, you are correct. But, FFT has only single clock. If i make the clock frequency of FFT as the sampling frequency of input signal then then the FFT computation time increases significantly for low sample rate input signal (eg: 5kSps). Unlike FIFO blocks, FFT does not have two separate clocks for input and output, so that i have flexibility to read, process and write at different clock frequencies. Is there any solution to just read the signal at lower sample rate but carry out FFT processing and writing at high clock frequencies ? Regards, Subash
  6. Hi, I am am able to compute the FFT using IP core block available in Vivado 2017. However, whatever is the sample rate of input signal to FFT IPcore, the frequency resolution of the FFT is fixed by clock frequency of the FFT. Example Frequency resolution = sampling frequency/number of samples DDS compiler generates sinusoidal frequency 976.56Hz at a clock freq of 1MHz,therefore the sample rate is 1Ms/s. this signal is given as input to the FFT IPcore 9.0 which is clocked at 5MHz with number of samples as 65536. therefore, Expected frequency resolution = 1MHz/65536, however
  7. Dear @[email protected] Sorry for the late reply; thanks for your responses. Your suggestions are helpful. i considered your suggestions 1 and 2 for square root, i simply delayed the m_axis_data_tuser by 33 samples using the same square root block. Regards, Subash
  8. Hi @[email protected] Thanks for your reply, I understood the difference between pipeline and burst modes. I figured out the reason for 33 samples delay between m_axis_data_tuser and m_axis_data_tdata. I used multiplier, adder and square root calculator to compute the magnitude of FFT which is sqrt(Re^2+Imag^2). The adder and multiplier took 2 clock cycle and the square root block (CORDIC) took 31 clock cycles. So, the output of m_axis_data_tdata is 33 clock cycles behind the m_axis_data_tuser. Do you have any better suggestions to calculate the magnitude of FFT which is sqrt(Re^2+Imag^2) wi
  9. Hi @[email protected] Hi [email protected], Thanks for your inputs, my responses are as follows. Do let me know, if i am not clear or has to provide further details. 1. I often counsel folks not to use burst mode, such as you are using, but the pipeline mode instead. This is due to the added logic and complexity of properly setting up the valid and ready wires on the input. Please see the attached image file of the design file. s_axis_data_tvalid is always set to 1. I am not concerned with the data loss during FFT computation 2. You never told me the sample rate (or clock rate
  10. Hi @[email protected] I went through the link provide by @jpeyron for FFT which is informative. I was able to perform FFT on the synthesized sine signals using DDS compiler. I tried FFT for various frequencies of sine signals and their details are as follows. FFT implementation: Radix-2 burst I/O, Natural order, 16384, 1 channel, Fixed-point, scaled, truncation, Use 3-multiplier structure, Use CLB-logic Sine signal 1: sampling frequency: 100kHz, Signal frequency: 48.828Hz, FIFO size:16384, Transform length: 16384, Frequency resolution: 100kHz/16384 Calculated BIN index
  11. Hi @jpeyron Thanks for your the link. I learned certain details about FFT and able to compute FFT using FFT IPcore V9.0. Regards, Subash
  12. Hi, I am trying to compute FFT of a synthesized square wave of frequency 100Hz. The 100Hz signal has to be sampled at 1kHz. So, I kept the clock frequency of FIFO, FFT_IPcore and other blocks at 1ms. I have attached the screenshot of the design file and simulation results. From the simulation output, it can be observed that the buffer stores for 512 samples and the un-buffer after 512*1ms. But, there is no output from the FFT block. I would like to know whether my approach is correct or I am committing any mistake in the way the blocks have to be integrated. Help much app
  13. Hi JColvin, Thanks, you are correct. Apparently the unused ADC pins should not be kept open. Th unused pins should be either grounded or connected to a external buffer circuits. If not somehow, the siganl given in one ADC pins is passed to other pins. Regards, Subash
  14. Hi JColvin, Yes i do. I connected all the N-pins to GND in the Pmod connector.