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Musko last won the day on June 11 2019

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  1. Thanks for pointers.
  2. I have ported the above also to RedPitaya. I had to do a bit of HW there too.
  3. Hi, For sw part I use Xilinx DMA driver (interface to VDMA IP core) and modified ADI AXI HDMI DRM driver for exposing frame buffer device to GUI sw (e.g. Qt). You can see driver bindings in above attached (pl.dtsi). All video memory transfers to FPGA are managed by this two drivers.
  4. Is it possible to get data from IIO devices to LabVIEW? Got few google hits, but none clear yes/no. IIO has bindings to Python and Matlab and both can (did experiment) source data from IIO devices. Libiio build/has also bindings for C#.
  5. The description of problem with wiring SPI via EMIO and SS_IO pin is in TRM chapter 17.5.4 (see IMPORTANT: note). The SS_IO pin is declared as signal type inout (bidirectional). See Vivado HDL processing_system7_0 wrapper file. It depends how you export SPI signals in Block Design, by default they are grouped together and exported as interface. The input part (SSIN) is used by Zynq SPI Master controller to detect multi-master mode. Have it float, the SPI Master controller can false detect multi-master mode. Note that Vivado Block Design validate will warn you with: WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream. One solution is to tie SSIN input to '1' (as described in Figure 17-8 in TRM) but you need to open and modify the Vivado HDL processing_system7_0 wrapper file, or export Zynq SPI pins as single signals and tie them in your top design. The other option is that on your HW you have an external pull up on this pin. The option I use (if HW does not have external pull up on this pin) is to add PULLUP constrain in xdc file (e.g. set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 PULLUP TRUE} [get_ports {spi0_ss_io}]). Another thing to mention here regarding possible problems for SPI via EMIO is that SPI max clock rate is lower (25Mhz vs 50MHz via MIO pins).
  6. I don't use Petalinux, never used it and also not familiar with its config/build files and procedures. I don't know what info Petalinux project-spec/config/ file contains. I build my own FSBL (from Vivado exported HDF file), U-Boot (from Xilinx git tag xilinx-v2017.3), LX kernel (from Xilinx git tag xilinx-v2016.4) and Buildroot (buildroot-2017.08.1) and than pack them to SD card (~16MBytes all together). I am attaching my LX kernel .config file (How my LX kernel is configured?). For video I don't use Xilinx DRM but modified ADI AXI HDMI DRM driver with (quite a lot) different encoder/connector part. The only Xilinx driver involved in my video driver stack is DMA driver (for VDMA IP core). I looked at Xilnx DRM driver first, but it was overkill (planes, re-samplers, format converters, display port, vtc re-config, ...) for what I need. Not using Xilinx DRM driver also gives me freedom on implementation of my FPGA video pipeline, e.g. my VTC in FPGA is hard configured to [email protected] All I need for my embedded video is a framebuffer for Qt application on fixed monitor resolution (SXGA [email protected]). I don't need xterm on my embedded Zynq. I use Qt-4.8.6 and Qwt-6.1.3 cross-compiled as static libraries (to ease Qt config on target). I start Qt application with -qws option which than use framebuffer device instead of X server. lx_kernel.config
  7. Thank you for info. In the meantime I managed to make it work with ADI AXI HDMI DRM driver by modifying it and combining it with Digilent encoder code. I use/build all involved drivers as loadable (insmod/rmmod) modules, so I was able to trace down all needed changes. Now it works perfectly with Xilinx VDMA with all other features (Plug-able EDID monitor detect, handling DPMS modes, ...). My GUI needs on ZyboZy-20 are satisfied with Qt and frame buffer (no need to extend to X infrastructure). Attached is device tree.
  8. I think the uio_dmem_genirq is missing compatible device tree driver definition and so it does not get probed. If you diff the two drivers you will see that at the end (inside CONFIG_OF def) there is missing module parameter named of_id: module_param_string(of_id, uio_of_genirq_match[0].compatible, 128, 0); MODULE_PARM_DESC(of_id, "Openfirmware id of the device to be handled by uio"); The technique used here is to pass the driver .compatible definition through module parameter (uio_pdrv_genirq.of_id=generic-uio). If you would load uio_pdrv_genirq via modprobe you would do it: modprob <path_to_driver>/uio_pdrv_genirq of_id=generic-uio The drivers .compatible definition is than matched to device tree entries and if found the driver is probed. For uio_dmem_genirq a device tree entry to put in, I think this one is OK for uio_dmem_genirq: [email protected] { compatible = "generic-uio"; num_dynamic_regions = <2>; dynamic_region_sizes = <0x8000>; interrupts = <0x0 0x1E 0x4>; interrupt-parent = <0x3>; clocks = <0x1>; }; The "uio,number-of-dynamic-regions" is different string than "num_dynamic_regions". But you can experiment or check what dev_get_platdata() function is expected. The answer is not complete copy/paste solution, but should point you to right direction.
  9. Thank you for welcome. Today was my first successful run of Qt GUI application on my ZyboZ7-20 after months of digging through the whole stack (FPGA - LX kernel - User Land). Currently I am trying to make frambuffer driver to start moving data via xilinx_dma driver. At the moment I have to program VDMA IP registers (MM2S_StartAdresses, MM2S_STRIDE, MM2S_HSIZE and MM2S_VSIZE) manually. There is something not yet ok in framebuffer driver and binding it with xilinx_dma driver. I will try with DRM driver (ADI or Xilinx as start point) since it is more decent technology as framebuffer. Once the project is in good shape I will consider adding it to Digilent project vault.
  10. Finally working! Brief description: On right monitor is ssh session from my devel PC to Zyboz7-20 where I start Qt applications (framebuffer and sysinfo on attached picture). Front monitor is connected to ZyboZ7-20 HDMI output port. Monitor resolution is SXGA ([email protected]). FPGA: - Build with Vivado 2016.4 - Data path for HDMI output: /dev/fb0 DDR image buffer --> Zynq AXI HP port --> AXI Protocol Converter IP (AXI3 to AXI4) --> VDMA IP (mm2s only) --> AXI4 Stream to Video IP --> Digilent RGB to DVI IP --> HDMI connector Video control signals are from Video Timing Controller IP (1280x1024p, Pixel clock is 108MHz). On SD card: - Boot image containing: FSBL, U-boot (Xilinx git tag xilinx-v2017.3), LX 4.6 kernel (configured and build from Xilinx git tag xilinx-v2016.4) and Buildroot-2017.08.1 - Modified Simple FrameBuffer driver. - Xilinx DMA driver. - My custom driver to control FPGA modules (VTC, Xilinx Performance monitor and some others I have in design). - Cross compiled Qt-4.8.6 examples (analogclock, framebuffer) and Qwt-6.1.3 examples (sysinfo, cpuplot). TODOs: - Simple FrameBuffer driver does not starts Xilinx DMA driver transfers, so I have to configure VDMA IP registers manually. But this is good enough for my first run and proof of concept. I will switch to and continue with DRM device driver. - Inputs (mouse and keyboard) to control Qt application.