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Everything posted by yassinema2018

  1. Okay it seems i can't connect directly thank you
  2. yassinema2018

    UART FTDI chip

    i tested a uart verilog design working great on the zybo at 9600 bits/s, i can communicante with externel MCU's, now i want to send and recieve some data from my laptop. for that i want to use the onboard ftdi chip on the zybo, is it possible to access to MIO pins and write uart data the chip inputs ? thank you
  3. Thank you sir i understand now
  4. is linking the 32 bits inputs the slv registers of the axi, tells vivado that no port wiring is required .? thank you
  5. thank you for replying editing the axi lite requires declaring the module with its inputs and linking the inputs to the slave registers ( i'm I wrong ???), so before doing that i need to get my module to work, the problem is i need two 32 inputs to my module so i can control the pwm up time and the pwm period, but when i declare the two inputs vivado tries to assign a physical port to each of the 64 bits and that's the problem because i don't need hardware ports to be assigned to them i just want to assign them to the slave registers
  6. YES i know but i can't figure out how to declare the 32 bit inputs so i can link them to the axi slave registers without vivado trying to place them to ports
  7. i'm trying to make a pwm module that i want to use later with the sdk the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....) as i understand vivado tries to give the two inputs a port with 64 bits my purpose is to assign a value to them from the sdk i tried declaring them as wires, integers, reg same error module pwm( input clk, input enable, output pwm_out, input [31:0]