• Content Count

  • Joined

  • Last visited

About tbrowning

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Following up on my post earlier: I was able to convert both projects to run on my custom Zynq PCB, but both of the projects failed to print out over UART still. I was able to get the LED working from the switch I addedto the design, but none of the PS code was running. Upon further investigation I found a big issue with the board: it is missing the PS_POR_B signal. I am not 100% sure that this is related to the PS project failing, but I'm not really sure what the function of the pin is other than a reset on power up and power down. Could anyone explain how this pin is suppose to
  2. I was able to get both of the methods I tried yesterday working this morning. Here is a short summary of my solution: 1) Created the block design using the ZYNQ PS with UART_1 enabled and an AXI UARTLite stream connected (see bd.png) 2) Modify the ZYNQ PS to send UART_1 to EMIO pins (see psconfig.png) 3) Modified the xdc file to route the 4 UART signals to the JC PMOD on the Zybo Z7. I also added a switch to turn on an LED for easier debugging (see xdc.png) 4) Set up a FSBL and HelloWorld application projects in SDK (see sdk.png) 5) Redirected stdin/stdout in the
  3. Hi @jpeyron, Thanks for the quick reply! I have tried playing around with this a bit; however, the forum you linked is using the MIO pins and the JF PMOD header which is already routed to the PS side of the Zynq. I was able to use this method for the Zybo board I have, but I would not be able to do this test with my custom PCB since none of the PMOD headers are connected to the PS side of the Zynq. For my first test I want to get UART1 connected to EMIO pins and then whatever logic is needed inbetween to route it out to the JC connector which is on the PL side of the Zynq. I tried j
  4. Hello, I am currently working on a project involving a custom ZYNQ PCB that was designed as a smaller version of the ZYBO Z7-20 board as part of a PCB class I taught at the University of Delaware. We got our boards back mid-April and have been testing them since. The board consist of the following features: - Dual HDMI (reconfigurable TX/RX with Digilent DVI cores) - 3 PMOD headers (1 high-speed, 2 general purpose) - 4 switches, 8 LEDs for GPIO - JTAG - SD - Flash - DDR So far everything besides the memory systems have been tested (SD/Flash/DDR); however, I made one
  5. Thank you for trying this out @elodg, currently the only messages I get are for the board.xit file where it can't read the f_xdc variable. I have the board files installed locally so I'm not sure if it is related to the board definition files, but if you could provide the tcl script I could try it, but I am not familiar with how to create such a file. I will try this setup on another machine to see if I can get different results.
  6. Hello @jpeyron, Would it be possible to have someone else revisit this topic? I tried @elodg suggestion with no luck, but I have a group of students who will try the same thing with multiple versions of Vivado to see if we can find one that works. I'm not sure what other options we have at this point
  7. Hello @elodg Thank you for the suggestion, I spent this morning/afternoon attempting to recreate the IP from the source files, but unfortunately ended with the same result... Once I get to the review and package stage and I re-package the IP I can see in the windows file explorer that there is a new utils folder created in the IPs directory containing the board.xit file leading to this error. I am not sure what to try next at this point. Can anyone confirm that they see the same behavior when repacking the dvi2rgb core?
  8. Good morning, I am currently working on a project that uses the DVI2RGB IP on a custom-built PCB like the zybo-z7 board (but uses the zynq 7020 like the zed board) and would like to make my own version of the IP for several reasons but have encountered the following errors: 1) My PCB board has 2 HDMI ports configurable as sink/source, however when using 2 instances of the DVI2RGB core I get the following error: (error1.png) 2) I would like to make a generic data protocol around the HDMI connector that doesn't require blanking and the DVI2RGB core is a nice, open-source platf