ariefgrand

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Everything posted by ariefgrand

  1. So that means petalinux doesn't support what I want by native? I have to use the IP Xillybus in my Vivado project. Thank you
  2. hi jamey, thank you very much for your reply. I tried using UIO in Petalinux and IT WORKS using a program based on the example from http://svenand.blogdrive.com/archive/203.html#.VSPCpeqm5pg !! But does it mean that I have to send the data 32-bits by 32-bits? What if I write the data in a file and then send it to /dev/uioX (e.g. using command "cat file.bin > /dev/uioX") ? Is that possible in Petalinux?
  3. Hi, Does anyone have ever sent data to AXI interfaces without using /dev/mem in Petalinux? I'm curious. I'm sure there is a way but I don't know how and I don't want to use a pointer that opens /dev/mem. I want to send a lot of data to several AXI components in the same time and I think using /dev/mem will give some problem. Thanks for your response.
  4. Hi Cristian, Thank you very much for your suggestion. Apparently, when we want to reprogram the PL part, we need to make a project in vivado, thus including PS part, with AXI interconnect. Not doing so will cause a crash in Linux, although the PL function you want to install will work in the board. I reprogrammed the FPGA successfully after including the PS part in Vivado project
  5. Hello guys, I'm working with Zybo SoC right now and I have a few questions which I couldn't find the answer anywhere. I am using petalinux in the card with the .bsp from digilent website (Petalinux 2014.2 Board Support Package). The thing is, I want to change/reprogram the PL many times but I want to do it from the Linux, e.g. using C program and configuration port /dev/xdevcfg. Is it possible to do it?When I use a command shell "cat <file-name>.bit > /dev/xdevcfg", I could reprogram the FPGA and I can see the result but I lost the control of the Linux. I couldn't access to the ARM via hyperterminal. Do you have any idea what cause this problem? Is that means when I reprogram the PL, I lose the PS part of the FPGA? Thank you very much for your response