RedMercury

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  1. Thanks @JColvin! I put some of the original numbers into a spreadsheet here, re-ordering the pins from alphabetical to numerical. Some questions: * Each pair has up to +/- 1.2mm delta, I assume this is within spec (which spec, heh) or accounted for by extra trace length in the FGPA? * Looking at these totals, I assume that each differential pair is only length matched as a pair and not for all pairs in the high speed PMOD port? e.g. if I have two differential data lines clocked to my differential clock, I’ll have to add some serpentine routing to the shortest pairs.
  2. Is the distance to the connector the distance to the through hole, or does it take into account the extra leg length for the top row of pins versus the bottom? Im designing a connector with two differential data lanes and a differential clock lane. Thanks!
  3. I’ll have a go tomorrow, but looking at the doc now PLL has a minimum frequency of 19Mhz, MMCM has a minimum frequency of 10Mhz. Sounds like that was the problem! Vivado could be a little more descriptive in its error messages..
  4. I'm trying to write a basic module for my Cmod A7 to poke around some pins on my oscilloscope. It seems to be impossible for me to create a PLLE2_BASE instance, I always get this error: [Netlist 29-73] Incorrect value '83.330002' specified for property 'CLKIN1_PERIOD'. The system will either use the default value or the property value will be dropped. Verify your source files. This is the offending piece of code: wire clk0; wire clk1; wire clk_fb; PLLE2_BASE #( .CLKFBOUT_MULT(2), .CLKFBOUT_PHASE(0.0), .CLKIN1_PERIOD(83.33), .CLKOUT0_DIVI
  5. Thanks - I found this snippet useful:
  6. Hi all, One of my projects is to make an HDMI output core driven by an AXI stream (rather than act as an AXI memory master). Since the video output is run by the pixel clock, it is in a different clock domain than the rest of the system. I understand that to cross the domain correctly I'd need a FIFO, and it seems that most async FIFO designs utilize gray codes to synchronize the read and write pointers, restricting the potential metastability bit error to one. Extrapolating this out, surely the number of potential bit errors increases when the frequencies are >2:1 (or some othe