Juan

I'm trying to figure out the reason, but I can't. I've run a functional simulation for both controllers, and the behaviour is the same. it's not simple for me I've even tried things like: if(start_operation)begin address_to_sram_output[18:0]<=address_input[18:0]; if(rw) begin state_reg <= rd0; end else begin register_for_writing_data[7:0]<=data_f2s[7:0]; state_reg <= wr0; end end What's the reason for that error?

you mean something like: https://github.com/salcanmor/SRAM-tester-for-Cmod-A7-35T/blob/master/basic controller v2/sram_ctrl6.v I've checked the resource utilization in both designs (sram_ctrl6.v and sram_ctrl5.v) and it is exactly the same. However, for some reason that I don't know, when I move out address_to_sram_output[18:0]<=address_input[18:0] just like you said, the initial message of my design get spoiled. This message is showed just after the bitstream is loaded (sram_ctrl6.v). The right message is (sram_ctrl5.v).

I've designed an improved version. It is the most efficient SRAM controller that can be done. It has an FSM with only 3 states. If possible, I would like to hear your opinion. Thanks in advance. Link: https://github.com/salcanmor/SRAM-tester-for-Cmod-A7-35T/blob/master/basic controller v2/sram_ctrl5.v

You're right. Thank you very much for your comments. I appreciate them very much. I've decided to make a more formal controller. Please take a look and share with me your comments: https://github.com/salcanmor/SRAM-tester-for-Cmod-A7-35T/blob/master/basic controller v2/sram_ctrl3.v I think this new version is a good starting point, isn't it? and now I'm going to work in making this controller more aggresive to be mucher closer to the timing parameters of the datasheet. Probably I will use the cloking wizard IP, to create a 100MHz, since I cannot be aggresive with a 12MHz clock. Finally, I will use the oscilloscope to demostrate how fast my controller is.

Hi guys, Some time ago, I asked here for a SRAM controller for the external SRAM of the Cmod A7 FPGA board. I've decided to make it myself. I've made a very basic and simple project. Next month, I will publish a much more precise and aggressive controller. I've documented everything and made a full project to test the SRAM in a friendly way. All the details (video, code, etc) here: https://www.hackster.io/salvador-canas/a-practical-introduction-to-sram-memories-using-an-fpga-i-3f3992

Hi guys, I have Cmod A7 35T and I don't know how to generate the .mcs file (Memory Configuration File) in Vivado 2018.2. Can anyone help me please? Thanks in advance.

Hi guys, According to the reference manual of the Cmod A7 (https://reference.digilentinc.com/_media/cmod_a7/cmod_a7_rm.pdf), the memory part is N25Q032A, but it is not included in Vivado 2018.2. Any help on this?

you mean CmodA735tDemoR1.zip, right?

I couldn't find any project with a Verilog controller for the SRAM.

Hi guys, I've just bought a Cmod A7-35T. It has an SRAM model IS61WV5128BLL-10BLI I would like to write a Verilog controller for this SRAM, but I don't have much info about how to do it. Can you help me please? I couldn't find any project on github to have it as reference. Thanks !!!

Hi all, Can you please tell me where can I find the Board definition file of Zybo Z7-20 for SDx ? I don't care about the SDx version. The only Board definition file of Zybo Z7-20 I found is the Vivado version one: https://github.com/Digilent/vivado-boards/tree/master/new/board_files/zybo-z7-20 Thanks

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