for six month I am learning VHDL, FPGA and related with an Artix-7 FPGA Development Board . Now I am trying to access the onboard DDR3 memory for reading and writing. For convenience I try to avoid writing my onw DDR3 Interface, so I was looking at several IP cores. My plan was configuring a suitable IP core and create an HDL Wrapper, so that I can access it from my VHDL code. I tried the Memory Interface Generator, but on the other end it has an AXI Slave Interface. So it seems that one interface I have to implement by myself.
Is there any simple solution or way, how to use DDR3 Memory? Something like Block Memory Generator provides. This interface is simple, which is easy to use for a beginne like me.