TommyK

Digilent Staff
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  1. Like
    TommyK reacted to kringg in Arty A7-100T DDR3-SDRAM Write Errors   
    For anyone else out there who's struggling with DDR3 SDRAM on the Arty A7, here's a project for Vivado 2019.2 that builds out-of-box and successfully reads / writes (via the MIG user interface) to / from memory. Hopefully this'll save someone the pain I went through figuring out how to interface with the DDR-SDRAM via Verilog.
    Arty-SDRAM.zip
  2. Like
    TommyK got a reaction from scw7t3 in iic setup failure   
    Its sounds to me like a memory issue as well. It looks to me like you are accessing the correct memory location. This isn't a problem with the cache. I think I've had issues with the Smart Connect IP before. Try recreating the block design without the Smart Connect IP.  Try running connection automation and unchecking the object (MIG?) that wants to add a SmartConnect IP.
     
    -Tommy
  3. Like
    TommyK got a reaction from jpeyron in DMC60c Default Settings   
    Default Device ID is 0, Current limit is disabled, continuous current limit 40A, peak current limit is 60A, current duration is 500ms. There is no voltage limit?
    All parameters and their defaults can be found in the DMC60C CAN Protocol Guide.
  4. Like
    TommyK got a reaction from jpeyron in DMC60c CAN Bus   
    Hi opethmc,
    The current and voltage information is reported by the DMC60C every 100ms (by default) in the STSANALOG (0x020614C0) frame. This info can be found on page 28-30 of the CAN protocol guide.
    Fault status can be found in byte 4 (fs2) in the STSGENERAL(0x02061400) frame that is sent every 10ms (by default). You can find the fault counts by reading parameters 51 through 57. This can be done by sending PARAMREQ (0x02061800) frames containing the parameter you want to read, then scanning for a PARAMRESP(0x02061840) packet.  This info can be found on page 12-28.
     
    Hope this helps!
    Tommy
  5. Like
    TommyK got a reaction from JColvin in cannot receive message from tx sender PMOD CAN and BASYS MX3   
    Hi Gaston,
    It looks like your CAN receiver doesn't have interrupts enabled. Try adding the following to the RX code, just above the readRegisters function in main()
    mcp25625_setRegister(MCP_CANINTE, 0x3);//Enable read buffer full interrupts mcp25625_setRegister(MCP_CANINTF, 0);//Clear interrupt flags Hope this helps!
    -Tommy
  6. Like
    TommyK got a reaction from victory460 in Arduino IDE Compiled SoftwareSerialExample failed   
    Hi @victory460,
    James was correct, it is an issue in the source code for the SoftwareSerial library. The PIC32MZEFG100 does not have an SIDL bit in the CNCON register like the older chips. You can get around this by commenting out those lines in SoftwareSerial.cpp for now. I have added an ifndef line to fix this in the Digilent Core v1.0.4 which i just uploaded.
    Hope this helps!
    Tommy
  7. Like
    TommyK got a reaction from davedisalvo in Xilinx AXI_GPIO Bug Fix   
    In Vivado versions 2015.X-2016.2 there is a bug in the AXI_GPIO Core when adding a board part to the GPIO2 interface on the AXI_GPIO IP block in Vivado IPI (block design). You may get the following error:
    [IP_Flow 19-3452] Invalid long/float value '16]' specified for parameter 'GPIO Width(C_GPIO2_WIDTH)' for BD Cell 'axi_gpio_0'.
    To fix this go into Vivado/2016.2/data/ip/xilinx/axi_gpio_v2_0/xgui/axigpio_v2_0.tcl and remove the extra ']' at the end of line 246.
    Hopefully Xilinx will fix this small typo in the 2016.3 release.
    Hope this helps!
  8. Like
    TommyK got a reaction from Shaw in Instantiating Nexys4 SRAM to DDR Component   
    Hi Warren,
    I have never tried working with .ngc files before, but you can copy the VHDL and MIG project files by first creating a project, with the Nexys4 DDR as the target board.
    Click "Add Sources"  Click the add design sources bullet and click next Click the green plus and select add files Find "Ram2Ddr_RefComp/Source/Ram2DdrXadc_Ref_Comp/ram2ddrxadc.vhdl", or the other source file (ram2ddr.vhd) if you are using the XADC in your project elsewhere. Once this is added, go back to "Add Sources" and select add existing IP Navigate to the same folder as before and go into ipcore_dir/ Select ddr.xco and click OK This will add the VHDL component and the IP core that Mihaita created for the Nexys4 DDR.
    Let me know if you have any other questions!
     
    Thanks,
    Tommy
  9. Like
    TommyK got a reaction from Retrobits in Xilinx AXI_GPIO Bug Fix   
    In Vivado versions 2015.X-2016.2 there is a bug in the AXI_GPIO Core when adding a board part to the GPIO2 interface on the AXI_GPIO IP block in Vivado IPI (block design). You may get the following error:
    [IP_Flow 19-3452] Invalid long/float value '16]' specified for parameter 'GPIO Width(C_GPIO2_WIDTH)' for BD Cell 'axi_gpio_0'.
    To fix this go into Vivado/2016.2/data/ip/xilinx/axi_gpio_v2_0/xgui/axigpio_v2_0.tcl and remove the extra ']' at the end of line 246.
    Hopefully Xilinx will fix this small typo in the 2016.3 release.
    Hope this helps!
  10. Like
    TommyK reacted to sy2002 in Is the Nexys 4 DDR to SRAM component really that slow?   
    Thank you for the hint about the looperdemo!
    (BTW: I already up-voted your first answer, but the system is showing this question still as "has no best answer" - no idea why)
     
  11. Like
    TommyK got a reaction from sy2002 in Is the Nexys 4 DDR to SRAM component really that slow?   
    Good luck! I used Mihaita's code to create a wider memory interface in my Nexys Video looper project. Take a look at it if you're having trouble! https://reference.digilentinc.com/nexys-video:looperdemo
  12. Like
    TommyK got a reaction from Commanderfranz in "Cannot erase chip"   
    Hi guys,
    Sorry you're have such a hard time with these boards. I'm pretty sure it's a problem with the old bootloader on the uC32. You can run the sketch found here in MPIDE to update the bootloader. You do not need a programmer to do this, just run the sketch in MPIDE and let me know if it solves the problem!
  13. Like
    TommyK got a reaction from [email protected] in Adept Asynchronous Parallel Interface Typo?   
    Hi Dan,
    Yes that is a typo. That signal should be called DSTB for both the Data write and Data read diagrams. Thank you for catching this. I'll do my best to get this corrected.
     
    Thanks
    Tommy
  14. Like
    TommyK got a reaction from davec in How to program Arty flash   
    Hi davec,
    Good catch. None of our other boards use configurable pins for the QSPI CCLK, so this one slipped through in the board files, I'll get it fixed asap.
    Next up, you'll need to create a bootloader to run your program out of DDR memory. There's a brief walkthrough here, but if you have problems, feel free to ask!
    Hope this helps!
  15. Like
    TommyK got a reaction from Commanderfranz in Arty_GSMB Memory Interface Generator   
    The tutorial has been updated. Good luck!
  16. Like
    TommyK got a reaction from Commanderfranz in netFPGA 1G original flash   
    Oops, wrong NetFPGA! I think you're going to want to look at this guide on the NetFPGA wiki to reprogram your NetFPGA. The files are hosted on their wiki here.
  17. Like
    TommyK got a reaction from Commanderfranz in XADC output for module instantiation   
    Hi Shruthi,
    I think you'll want to make a small state machine to accomplish this. 
    reg [2:0] state=0'b000;
    [email protected](posedge(clk)) begin
    switch(state):
        case 0: begin
                     do stuff
                     state<=1
       case 1: begin
                    (and so forth)
                     etc...
    endcase
    end
  18. Like
    TommyK got a reaction from Commanderfranz in VIVADO 15.4 DIGILENT zybo board not recognizing   
    Hi Thays,
    I'll install a copy of linux and try to get to the bottom of this.
  19. Like
    TommyK got a reaction from sLowe in HDM In EDID ROM default file?   
    Hi Randall,
    Unfortunately the documentation is not up to date, so I notified someone who can fix that. In order to change the EDIDs, you can download a program (it's a single .exe file) called Phoenix EDID Designer. This gives you a GUI which allows you to change the ****_edid.dat files found in the dvi2rgb_v1_6/docs folder. There's a .cpp script in there that can be run to generate the ****_edit.txt files. These files are then selected in the IP core. I'm not sure, but I think you'll need to overwrite one of the .txt files if you want it to be seen in the IP core.
  20. Like
    TommyK got a reaction from sLowe in Revision Control for Vivado   
    Hi Steve,
    We only have some very loose instructions on creating these projects. You can basically read through the create_project.tcl script found in the /proj folder to see how it works. It basically creates a new project and adds the other folders as Vivado repos. If there is a block design it runs that tcl script as well. All you would really need to do is make a copy and replace the files in there with your own files.
  21. Like
    TommyK got a reaction from sLowe in netFPGA 1G original flash   
    Oops, wrong NetFPGA! I think you're going to want to look at this guide on the NetFPGA wiki to reprogram your NetFPGA. The files are hosted on their wiki here.
  22. Like
    TommyK got a reaction from sLowe in netFPGA 1G original flash   
    Hi rfrm,
    I found this .mcs file which you can program to the QSPI flash.
  23. Like
    TommyK got a reaction from Randall Aiken in HDM In EDID ROM default file?   
    Hi Randall,
    Unfortunately the documentation is not up to date, so I notified someone who can fix that. In order to change the EDIDs, you can download a program (it's a single .exe file) called Phoenix EDID Designer. This gives you a GUI which allows you to change the ****_edid.dat files found in the dvi2rgb_v1_6/docs folder. There's a .cpp script in there that can be run to generate the ****_edit.txt files. These files are then selected in the IP core. I'm not sure, but I think you'll need to overwrite one of the .txt files if you want it to be seen in the IP core.
  24. Like
    TommyK reacted to Mehdim in How to use Audio on Zybo board   
    Thanks Tom. finally i could debug and resolve it.
    I will try to put some document and file about it here so everyone can use it.
     
  25. Like
    TommyK got a reaction from Mehdim in How to use Audio on Zybo board   
    I'm afraid I can't be of much help here. If your I2C is confirmed working, then the only thing to look at is the I2S controller. Make sure your pins are mapped out correctly in the xdc contraints file. Maybe check out the i2s_ctl.vhd file in the looper demo and compare it to the one from the instructables. I haven't gone through the instructable so I don't know what could be wrong, but I can try it out when I find time.