TommyK

Digilent Staff
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Everything posted by TommyK

  1. TommyK

    Eclypse-Z7 FPGA Fan

    @zygot, I pushed the fixes an hour ago. The fixed code was tested on hardware and works. The initial commit was somewhat rushed to get you something to work with as soon as possible. I apologize for the inconvenience it may have caused.
  2. Have you tried simulating your design? You can download the MT41K128M16JT-125 verilog memory model from Micron's website under simulation models (direct link). Place the model files into your sim sources and connect the DDR pins in the top level of your test bench code to the ddr module included in the memory model files. This will make debugging much faster for you. -Tommy
  3. Hey @asmi, Thanks for notifying us on this. While the settings before worked, they weren't optimal. I've changed the mig.prj in the Genesys2 board file to your recommendations. I'm not sure why VccAuxIO was set to 1.8V, the setting is not changeable in the MIG and must default to that value. Either way it's fixed now. Thanks, Tommy
  4. TommyK

    iic setup failure

    Glad it worked!
  5. TommyK

    iic setup failure

    Its sounds to me like a memory issue as well. It looks to me like you are accessing the correct memory location. This isn't a problem with the cache. I think I've had issues with the Smart Connect IP before. Try recreating the block design without the Smart Connect IP. Try running connection automation and unchecking the object (MIG?) that wants to add a SmartConnect IP. -Tommy
  6. TommyK

    DMC60c CAN Bus

    Yes I think so. As long as the controller ACKs the messages coming from the DMC60C it will continue to send the messages.
  7. TommyK

    DMC60c CAN Bus

    DMC60C is 1MBps. No, those green and yellow wires are connected together, either CAN or PWM, not both. The DMC60C must be connected to a CAN bus controller to send out the periodic messages. Otherwise it will flash red. When it detects a CAN bus controller the LEDs will flash Yellow (by default). -Tommy
  8. Default Device ID is 0, Current limit is disabled, continuous current limit 40A, peak current limit is 60A, current duration is 500ms. There is no voltage limit? All parameters and their defaults can be found in the DMC60C CAN Protocol Guide.
  9. TommyK

    DMC60c CAN Bus

    Hi opethmc, The current and voltage information is reported by the DMC60C every 100ms (by default) in the STSANALOG (0x020614C0) frame. This info can be found on page 28-30 of the CAN protocol guide. Fault status can be found in byte 4 (fs2) in the STSGENERAL(0x02061400) frame that is sent every 10ms (by default). You can find the fault counts by reading parameters 51 through 57. This can be done by sending PARAMREQ (0x02061800) frames containing the parameter you want to read, then scanning for a PARAMRESP(0x02061840) packet. This info can be found on page 12-28. Hope t
  10. Hi Brian, Unfortunately there is no easy way to slow down the packets transmitted by the vcmdGetDescriptors command without changing the firmware. It sounds like this is more an issue with the CANable device. I don't think there is much we can do for you here. -Tommy
  11. Hi Kabron, I just tried installing both Digilent and ESP8266 board support packages and it seems like mine installed just fine. In your post on the VM forums, it sounds like they both work in Arduino, but not in Visual Micro. Is that the case? I do not think it has anything to do with the Digilent core. What happens is Arduino reads the json file from the URL you give it. It then downloads each component as .zip files into %localappdata%/Arduino15/staging/packages/ . These are then unzipped and placed in %localappdata%/Arduino15/packages/Digilent. That is all it does. I'm guessing Vi
  12. Hi Gaston, It looks like your CAN receiver doesn't have interrupts enabled. Try adding the following to the RX code, just above the readRegisters function in main() mcp25625_setRegister(MCP_CANINTE, 0x3);//Enable read buffer full interrupts mcp25625_setRegister(MCP_CANINTF, 0);//Clear interrupt flags Hope this helps! -Tommy
  13. Hi @victory460, James was correct, it is an issue in the source code for the SoftwareSerial library. The PIC32MZEFG100 does not have an SIDL bit in the CNCON register like the older chips. You can get around this by commenting out those lines in SoftwareSerial.cpp for now. I have added an ifndef line to fix this in the Digilent Core v1.0.4 which i just uploaded. Hope this helps! Tommy
  14. Check out this project on Instructables. It's doing exactly what you're talking about.
  15. Hi Philip, Thanks for pointing that out. It must have slipped past when I was transferring files over OSes. The checksum and file have been updated and should work now. If you still get the CRC error, delete the old xc32-tools found in /users/[name]/Library/Arduino15/staging/packages and try again. Thanks, Tommy
  16. Woah, I apologize for not getting back sooner. I thought I had responded to this a while ago! All you need to do to update the firmware is run the sketch https://reference.digilentinc.com/_media/chipkit_uc32/updbluc32.zip in MPIDE. This will update the firmware to be used in Arduino IDE WITHOUT the use of a PicKIT3 or another debugger. Open the sketch and program your board. When it is programmed, open the serial monitor and follow the instructions there to install the firmware update. Hope this helps!
  17. Hi testweenie, I would love to see this feature as well, although I'm not sure if it will be possible with this release. I'll forward this to our engineers and see what they have to say.
  18. Hah, my bad, deleted my first post. I'm not sure if it would make any difference, but you could try scoping it in Scope mode. There you can add a digital channel, but it will still sample at whatever frequency you have it set to sample at. You might try making a measurement script in the scope mode as well, although I've never tried it before. I would imagine that you can log the data every 8 clocks and save it to a file. You could also try logging the data in the logic analyzer with a high sample rate. You can find this in View>Logging. I would suggest simply slowing down the clock sp
  19. In Vivado versions 2015.X-2016.2 there is a bug in the AXI_GPIO Core when adding a board part to the GPIO2 interface on the AXI_GPIO IP block in Vivado IPI (block design). You may get the following error: [IP_Flow 19-3452] Invalid long/float value '16]' specified for parameter 'GPIO Width(C_GPIO2_WIDTH)' for BD Cell 'axi_gpio_0'. To fix this go into Vivado/2016.2/data/ip/xilinx/axi_gpio_v2_0/xgui/axigpio_v2_0.tcl and remove the extra ']' at the end of line 246. Hopefully Xilinx will fix this small typo in the 2016.3 release. Hope this helps!
  20. The onboard OLED has been added to the Genesys2 board files. It is treated like a Pmod and works with our PmodOLED IP core. Hope this helps!
  21. I'm not entirely clear on what you mean. The JTAG-HS2 MOSI and MISO pins are designed as one directional pins, so trying to send a signal TO the TDI pin will not do anything. Same thing goes for trying to receive from TDO.
  22. Hi Kilrah, This is a known issue with the tcl script formats that we are using. Fortunately in this case we can change one line in the block design script file to get it to work. Open ZYBO/Projects/hdmi_in/src/bd/system.tcl. On line 13, change 2015.4 to 2016.2 and save it. You should now be able to generate it in 2016.2 Hope this helps!
  23. TommyK

    Genesys2 demo project

    Hi guys, I've updated the Genesys2 user demo to work with 2015.4. I don't have much say in how we are packaging the projects up, but I've told some higher ups. Thanks, Tommy
  24. From what I understand, I think the Spartan-6 series FPGAs included the memory interface, and you only neded to create a wrapper for it to work. The Artix-7 has more generic components which allows the FPGA to interface with many more types of memory if needed. This means Xilinx created a MIG to implement this in hardware. You can see all of the internal clocks the MIG uses in the Summary page if you double click the MIG block in your design. As for your second question, yes there will be a bit of latency in crossing the clock domains, but you are still getting almost exactly the same per
  25. Hi digitalone, The DDR3 on the Arty is actually running much faster, at about 667Mhz, it is just parallel data sampled at a slower rate. I'm pretty sure the memory interconnect samples 128bits of data at 83.3Mhz (the data bus is 16 bits wide). I'm not entirely sure, but in theory you might be able to clock the DDR3 slower to make the ui_clk run at 100Mhz, but you'd be losing a lot of performance, and I think there is a small bug in the MIG that doesn't allow this.