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tom21091 last won the day on March 9 2017

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About tom21091

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  • Birthday 02/10/1991

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  1. Hi Gaston, It looks like your CAN receiver doesn't have interrupts enabled. Try adding the following to the RX code, just above the readRegisters function in main() mcp25625_setRegister(MCP_CANINTE, 0x3);//Enable read buffer full interrupts mcp25625_setRegister(MCP_CANINTF, 0);//Clear interrupt flags Hope this helps! -Tommy
  2. Hi @victory460, James was correct, it is an issue in the source code for the SoftwareSerial library. The PIC32MZEFG100 does not have an SIDL bit in the CNCON register like the older chips. You can get around this by commenting out those lines in SoftwareSerial.cpp for now. I have added an ifndef line to fix this in the Digilent Core v1.0.4 which i just uploaded. Hope this helps! Tommy
  3. tom21091

    Zybo Zynq Guitar effects

    Check out this project on Instructables. It's doing exactly what you're talking about.
  4. Hi Philip, Thanks for pointing that out. It must have slipped past when I was transferring files over OSes. The checksum and file have been updated and should work now. If you still get the CRC error, delete the old xc32-tools found in /users/[name]/Library/Arduino15/staging/packages and try again. Thanks, Tommy
  5. Hy,

    Sorry to bother you. I've seen that you've been working with  PmodOLEDRGB.

    I tried to make the tutorial "Getting the PmodOLEDrgb to work on Zybo" available on the website to work for Zedboard. When I program the FPGA and run the application nothing gets displayed on the OLEDrgb Pmod.


    Are there any setup steps that need to be done?

    I have no error messages and no warnings.


    Best regards,Cris

  6. tom21091

    "Cannot erase chip"

    Woah, I apologize for not getting back sooner. I thought I had responded to this a while ago! All you need to do to update the firmware is run the sketch in MPIDE. This will update the firmware to be used in Arduino IDE WITHOUT the use of a PicKIT3 or another debugger. Open the sketch and program your board. When it is programmed, open the serial monitor and follow the instructions there to install the firmware update. Hope this helps!
  7. tom21091

    AD2 logic analyzer mode

    Hi testweenie, I would love to see this feature as well, although I'm not sure if it will be possible with this release. I'll forward this to our engineers and see what they have to say.
  8. tom21091

    AD2 logic analyzer mode

    Hah, my bad, deleted my first post. I'm not sure if it would make any difference, but you could try scoping it in Scope mode. There you can add a digital channel, but it will still sample at whatever frequency you have it set to sample at. You might try making a measurement script in the scope mode as well, although I've never tried it before. I would imagine that you can log the data every 8 clocks and save it to a file. You could also try logging the data in the logic analyzer with a high sample rate. You can find this in View>Logging. I would suggest simply slowing down the clock speed when debugging. Hope this helps!
  9. tom21091

    Xilinx AXI_GPIO Bug Fix

    In Vivado versions 2015.X-2016.2 there is a bug in the AXI_GPIO Core when adding a board part to the GPIO2 interface on the AXI_GPIO IP block in Vivado IPI (block design). You may get the following error: [IP_Flow 19-3452] Invalid long/float value '16]' specified for parameter 'GPIO Width(C_GPIO2_WIDTH)' for BD Cell 'axi_gpio_0'. To fix this go into Vivado/2016.2/data/ip/xilinx/axi_gpio_v2_0/xgui/axigpio_v2_0.tcl and remove the extra ']' at the end of line 246. Hopefully Xilinx will fix this small typo in the 2016.3 release. Hope this helps!
  10. tom21091

    genesys 2 board file missing oled support

    The onboard OLED has been added to the Genesys2 board files. It is treated like a Pmod and works with our PmodOLED IP core. Hope this helps!
  11. tom21091

    Can the JTAG HS2 do Dual I/O SPI?

    I'm not entirely clear on what you mean. The JTAG-HS2 MOSI and MISO pins are designed as one directional pins, so trying to send a signal TO the TDI pin will not do anything. Same thing goes for trying to receive from TDO.
  12. tom21091

    1080i hdmi input with zybo

    Hi Kilrah, This is a known issue with the tcl script formats that we are using. Fortunately in this case we can change one line in the block design script file to get it to work. Open ZYBO/Projects/hdmi_in/src/bd/system.tcl. On line 13, change 2015.4 to 2016.2 and save it. You should now be able to generate it in 2016.2 Hope this helps!
  13. tom21091

    Genesys2 demo project

    Hi guys, I've updated the Genesys2 user demo to work with 2015.4. I don't have much say in how we are packaging the projects up, but I've told some higher ups. Thanks, Tommy
  14. tom21091

    ARTY MicroBlaze Running at 100MHz

    From what I understand, I think the Spartan-6 series FPGAs included the memory interface, and you only neded to create a wrapper for it to work. The Artix-7 has more generic components which allows the FPGA to interface with many more types of memory if needed. This means Xilinx created a MIG to implement this in hardware. You can see all of the internal clocks the MIG uses in the Summary page if you double click the MIG block in your design. As for your second question, yes there will be a bit of latency in crossing the clock domains, but you are still getting almost exactly the same performance. You can find all of the nitty-gritty details in the 7-Series MIG User Guide, but I'm sure that you are getting the best performance possible as it is. Don't forget, you can also enable caching in the Microblaze! I hope this helps!
  15. tom21091

    ARTY MicroBlaze Running at 100MHz

    Hi digitalone, The DDR3 on the Arty is actually running much faster, at about 667Mhz, it is just parallel data sampled at a slower rate. I'm pretty sure the memory interconnect samples 128bits of data at 83.3Mhz (the data bus is 16 bits wide). I'm not entirely sure, but in theory you might be able to clock the DDR3 slower to make the ui_clk run at 100Mhz, but you'd be losing a lot of performance, and I think there is a small bug in the MIG that doesn't allow this.