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  1. Another thing to note before running Synthesize and Implement Design is to make sure that the UCF file is on the top level. Otherwise it will give you the same warning about I/O Standard, which prevents you from finishing the compilation.
  2. Hi Hamster, The magic fix was what you mentioned, to have the following settings for a new project: Family: Artix 7 Device: XC7A100T Package: CSG324 Speed: -1 Here are the steps to get a simple design up and running. Download Master UCF file from Nexys 4 DDR product page and save it to a directory you can find it Create your design and assign I/O markers In the Design Heirarchy side-menu, right-click on the top-level (xc7a100t-1csg324), click Add Source, and select the Master UCF file that was downloaded from the product page Double-click on the downloaded UCF file and uncomment the I/O ports you wish to use for your design Change the net name of the I/O pin to the net name you assigned on the schematic Run Synthesize - XST, Implement Design, and Generate Program file (bit file) Run Digilent Adept, connect the USB cable to the N4-DDR, and power on the board The N4-DDR should now be visible on Digilent Adept In the Config tab, select the generated bit file (from ISE 14.5), and click Program Test your design using the I/Os you specified in the UCF file
  3. Thanks a lot Alex and Hamster, I got it working. The initial configuration was a bit confusing, now I can move on to more complex designs.
  4. Hi Alex, I removed the ibufs and obufs and added the downloaded UCF file (Nexys4DDR_Master.ucf). I uncommented the I/Os that I'm using (SW0, SW1, SW2 and LD0). I figured that the net name mapped to the pin would be whatever I named the net in the schematic, in this case, A, B, C, and F. For example, in the UCF file, it reads NET "A" LOC=J15 | IOSTANDARD=LVCMOS33; Going back to the processes, I'm able to Synthesize and Translate, but fails when it gets to Map and I get the following error messages: ERROR:MapLib:30 - LOC constraint L16 on B is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:30 - LOC constraint M13 on C is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:30 - LOC constraint H17 on F is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. I also tried changing the net-names back to the default values (e.g. "sw<0>, sw<1>, etc"), but it didn't help.
  5. Hi Alex, Thanks for pointing it out. What directory should I put the master UCF file in? I looked in the directory where all of my project files are stored and saw a UCF file (named after my schematic file). Should I replace that file with the Master file and rename it? Previously when I designed with the Basys (1st gen) board, I would map I/O pins using ibuf and obuf. If I wanted to map the input to Pin 15 on the board, I would say LOC = P15. In this case, is using ibuf and obuf the right way to map IO pins (e.g. LOC = J15 --> Pin J15)? If I wanted to map an input to Pin J15, would I say LOC = PJ15 or LOC = J15? What's the correct way of doing this?
  6. I recently got a Nexys 4 DDR and I'm trying to get started with a simple switch/blink-LED program. I'm using ISE Design Suite 14.5 (nt64) and I'm getting warning messages that's preventing the design from completely compiling. This is what I tried: Created a very simple design (in schematic mode) using three switch inputs, an LED output, and basic logic (AND & NAND)Added 3 ibuf, one for each input and an obuf for the outputAssigned each ibuf/obuf pin numbers from reference manual (e.g. LOC = J15)Added I/O markers, labeled A, B, C (inputs), and F (output)Get the following warning messages during compile (Implement Design > Map)WARNING:LIT:701 - PAD symbol "A" has an undefined IOSTANDARD.WARNING:LIT:702 - PAD symbol "A" is not constrained (LOC) to a specific locationThus, I'm unable to generate a Programming File (bit file?)What am I doing wrong? Am I missing a step? This was pretty much the same procedure I followed when I worked with the first-gen Basys board, using an older version of ISE (9.2), and I was able to do much more complex designs with no problems. From what I understand, I would create a design in ISE 14.5, compile it using Synthesize-XST, Implement Design, and Generate Programming File (bit file?). Then I would send the bit file to the Nexys 4 DDR using Digilent Adept? Should I start using the Vivado Design Suite? I heard it's like $2000+ for a license. I also heard there's a device-limited license?