Jan Kok

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Everything posted by Jan Kok

  1. This post is to report a problem and a workaround. My setup: A few weeks ago I installed Vivado 2016.4 and am using an Arty Z7-20 board. I've been working through the Getting Started with the Vivado IP Integrator tutorial https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. At Section 8.3 where I try to run the demo by clicking Run As > Launch on Hardware (System Debugger), I got "Error while launching program: Memory write error at 0x100000. APB AP transaction error, DAP status f0000021" It turned out that I had the Boot Mode jumper (JP4 on the Arty Z7) set to QSPI. After moving the jumper to JTAG, resetting the board (by pressing the PORB button), clicking Xilinx Tools > Program FPGA > Program, and then clicking Launch on Hardware, the program loaded and ran. Editing the main.c program and clicking Launch on Hardware worked. Problem solved, right?! Well, not so fast... If I Program FPGA again without first resetting the board, and then Launch on Hardware, I get any of several errors: Memory write error at 0x100000. APB AP transaction error, DAP status f0000021 AP transaction error, DAP status f0000021 Memory write error at 0x100000. AP transaction timeout Once one of those errors has occurred, repeating Launch on Hardware will always get an error, not necessarily the same error each time. By the way, Program FPGA without first resetting the board never gives any error indication and always turns off and then on the DONE LED. That's not good. It should at least report an error. If I press the SRST button and then Program FPGA, I get a popup error: "Program FPGA failed / Cannot find memory context of target ARM_DAP". If I press the PORB button (or power cycle the board), then Program FPGA, then Launch on Hardware, the launch is successful, and repeatedly launching continues to succeed. So, the full workaround to AP transaction errors after Launch on Hardware is: 1. Make sure the boot mode jumper is set to JTAG, and 2. Press the PORB button, then Program FPGA. Launch on Hardware should then work.
  2. Hi @zygot, thanks for sharing your thoughts on this subject. I'm making some progress with getting myblock to work. Now I can connect it, but I'm getting some warnings and errors that I'm trying to resolve. Another approach might be to modify an axi_gpio block, adding my own logic and removing stuff I don't need such as interrupt logic. That would be similar to what you mentioned (creating your own IP), except I would start with known working code rather than developing a new block from scratch. What learning materials did you use to figure out how to make your own IP? I do like the IP Integrator, mainly because the block diagram is much more compact (one page) and comprehensible compared with 1500 lines of Verilog in block_design.v.
  3. Jan Kok

    Array

    Indeed! Where do all those numbers that you want to add come from? They probably come from some shared memory or from some input ports. The shared memory or I/O ports are likely to be the main bottleneck limiting your design's performance.
  4. Jan Kok

    Array

    In VHDL, "generate" will probably do what you want. Not sure what the equivalent thing is in Verilog.
  5. The connection between axi_gpio_1 and rgb_led is a bundle of 3 busses: gpio2_io_i, gpio2_io_o, and gpio2_io_t. That is revealed by clicking on the "+" sign next to GPIO2 in the block diagram (in my screen shot, the + sign has turned into a - sign). Since GPIO2 is a bundle and inbus is a simple bus, the bus structures don't match, and the block diagram editor won't let me connect them together, and for the same reason won't let me connect outbus with rgb_led. So one question is, how can I make myblock have ports that can be connected with axi_gpio_1 and rgb_led? Another question is, how can I tell what the structure of the rgb_led input port is? There is no "+" sign that I can click on. Thanks for the recommendations for more learning material. These look great. I'll start reading them.
  6. I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its ports are compatible and I can connect myblock between axi_gpio_1 and rgb_led? A more general question: what would you recommend as a next level of tutorial to study so that I wouldn't have to ask the questions above? I've looked on the Xilinx site, but the amount of documentation is overwhelming. I don't know where to start! Here is myblock.v and part of my block diagram:
  7. I'm about to install Vivado on a new computer and want to know which version(s) will work for compiling the Arty Z7 and Arty A7 example projects. I'm asking because I've tried to use version 2017.4 twice and had problems each time, possibly due to version incompatibility problems. Using version 2016.4 resulted in success each time. In another thread, @jpeyron said "The xadc project was made for Vivado 2016.4. Unfortunately, the version does matter." Unfortunately, the "Installing Vivado and Digilent Board Files" document https://reference.digilentinc.com/vivado/installing-vivado/start (which is referenced at https://reference.digilentinc.com/reference/programmable-logic/arty/start?redirect=1, https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start, https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start, and probably lots of other project "start" pages) recommends using "Vivado Design Suite - HLx Editions - 2017.4 Full Product Installation"! So, does the 2017.4 HLx edition work with the Arty Z7 and A7 example projects? If not, the "Installing Vivado and Digilent Board Files" document contains bad advice, which can lead to users wasting hours or days of their time downloading and installing the software and then trying to get the projects to work. Please clarify which Vivado versions and Editions (plain Vivado vs. HLx) work with the example projects.
  8. Hallelujah!!! The XADC demo built and is now running on my Arty Z7-20 board. Thank you, thank you, thank you, @jpeyron !!! The problem was, in the Arty-Z7-20-xadc-2016.4-2.zip (239 KB) file I was using, the repo/Vivado-library folder contained the ip folder only, and that ip folder only had 1.3MB of stuff, when unzipped. The vivado-library-c78277642564934f23b19a086bc575d49653558d that Jon pointed me to (https://github.com/digilent/vivado-library/tree/c78277642564934f23b19a086bc575d49653558d ) is about 170 MB - so a few things were apparently missing from the Arty-Z7-20-xadc-2016.4-2.zip I originally used! I probably got the too-small zip file by clicking the download zip file link in https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start (under Projects Supported by this Tutorial) or https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-xadc-demo/start (under Downloads). The GitHub links download even smaller XADC demo folders, with nothing at all in their vivado-library folders. Digilent folks: please fix the documentation or the downloads so that the next newbie doesn't fall into the same man-trap I fell into. Also... I haven't tried building again with Vivado 2017.4, but if there are substantial problems with using the later versions, then there should be stronger and more prominent warnings in the documentation about which Vivado versions to use. Earlier this year when I was getting started with my Arty 35T, I started by installing the latest Vivado release. I wasted a day or two trying to get a demo working with the latest Vivado. Finally gave up and installed an older Vivado, which worked. Now I've had the same experience again (downloading multiple versions of Vivado) with my Arty Z7. Please make your documentation more newbie-friendly! Save time for your users, and for yourselves (fewer questions to answer on this forum). Thanks.
  9. "I was describing the window command file cleanup as shown" Yeah, I figured that out eventually :-) So I just created a new work folder c:/Users/janko/Vivado6 and copied Arty-Z7-20-xadc in there, copied all the "new" board files to c:\Xilinx\Vivado\2016.4\data\boards\board_files, then started Vivado 2016.4 and tried to create the project. This is what I got: start_gui cd c:/Users/janko/Vivado6/Arty-Z7-20-xadc/proj/ source ./create_project.tcl # set proj_name "XADC" # if {[info exists ::create_path]} { # set dest_dir $::create_path # } else { # set dest_dir [file normalize [file dirname [info script]]] # } # puts "INFO: Creating new project in $dest_dir" INFO: Creating new project in C:/Users/janko/Vivado6/Arty-Z7-20-xadc/proj # cd $dest_dir # set part "xc7z020clg400-1" # set brd_part "digilentinc.com:arty-z7-20:part0:1.0" # set origin_dir ".." # set orig_proj_dir "[file normalize "$origin_dir/proj"]" # set src_dir $origin_dir/src # set repo_dir $origin_dir/repo # create_project $proj_name $dest_dir INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'. # set proj_dir [get_property directory [current_project]] # set obj [get_projects $proj_name] # set_property "default_lib" "xil_defaultlib" $obj # set_property "part" $part $obj # set_property "board_part" $brd_part $obj # set_property "simulator_language" "Mixed" $obj # set_property "target_language" "VHDL" $obj # set_property "corecontainer.enable" "0" $obj # set_property "ip_cache_permissions" "read write" $obj # set_property "ip_output_repo" "[file normalize "$origin_dir/repo/cache"]" $obj # if {[string equal [get_filesets -quiet sources_1] ""]} { # create_fileset -srcset sources_1 # } # if {[string equal [get_filesets -quiet constrs_1] ""]} { # create_fileset -constrset constrs_1 # } # set obj [get_filesets sources_1] # set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj # update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/janko/Vivado6/Arty-Z7-20-xadc/repo'. ERROR: [Common 17-39] 'update_ip_catalog' failed due to earlier errors. while executing "update_ip_catalog -rebuild" (file "./create_project.tcl" line 69) It's complaining about parts, not boards. Why can't it identify those parts? Should I try uninstalling Vivado and/or SDSoC and then install Vivado 2016.4 once more? That would take me about 1 1/2 hours. Thanks!
  10. Thanks for getting back! "First go to the proj folder and double click cleanup." Um... what file browser should I use to go to the proj folder? I'm asking because I don't see a cleanup button anywhere that I can double click on. Meanwhile, I'll try deleting and reinstalling the xadc demo. I just noticed that I have two identical-looking Vivado 2016.4 icons in my start menu. When I click one of them, I see "Vivado 2016.4" in the title bar. When I click the other one, I see "Vivado 2016.4_sdx" in the title bar. I had been using the sdx one. I'm guessing that was supplied when I installed SDSoC 2016.4, and the non-sdx one was installed when I later installed Vivado 2016.4. I guess that explains why I didn't see C:\Xilinx\Vivado\2016.4 folder until I installed Vivado 2016.4 directly.
  11. Any further help with this? As mentioned in my previous post in this thread, I'm still stuck, with both 2016.4 and 2017.4 versions of Vivado. Thanks.
  12. Hi @jpeyron, thanks for reply. In the case of Vivado 2017.4, I did install the arty-z7-20 board files only - not the other board files in the zip file. (Do I need to install the others?) In the case of Vivado 2016.4, I forgot to install the board files. When I looked for them (after writing the note that begins this thread), I was surprised that there was no C:\Xilinx\Vivado\2016.4 directory at all! Though there was a C:\Xilinx\Vivado\2017.4 directory. It was surprising, because there was a Vivado 2016.4 icon in my Start menu (as a result of installing SDSoC 2016.4), and clicking that icon actually started Vivado 2016.4 and let me get as far as I did. Very confusing, how could that work?! Anyway, since the Vivado\2016.4 directory was missing, I installed Vivado 2016.4, which created the Vivado\2016.4 directory and lots of stuff under it, and installed the arty-z7-20 board files, then tried to build the xadc demo again. I got similar results as before, # update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' (etc.) I got the XADC demo from a zip file. It does contain repo\vivado-library and a bunch of stuff under that. And yes, I've been careful to select Arty-Z7-20 (not -10) where appropriate. So I'm still stuck. Any ideas on how to proceed with either Vivado 2016.4 or 2017.4?
  13. I tried to build the XADC example project using Arty-Z7-20-xadc-2016.4-2.zip , https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-xadc-demo/start , and https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start . Using Vivado 2016.4, after entering the tcl command "source ./create_project.tcl" I get ...# update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2406] Cannot identify part xc7a200tsbg484-1 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7a15ticsg324-1L ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' (etc.) Using Vivado 2017.4, I get a lot farther. I clicked Generate Bitstream. While launching implementation run, I got a critical warning: [IP_Flow 19-4739] Writing uncustomized BOM file 'c:/Users/janko/Xilinx/Arty-Z7-20-xadc/src/ip/xadc_wiz_0/xadc_wiz_0.xml' The build subsequently failed. I found an answer (AR# 69645) on the Xilinx site related to the IP_Flow 19-4739 warning, but it wasn't helpful. There is indeed a file C:\Users\janko\Xilinx6\Arty-Z7-20-xadc\src\ip\xadc_wiz_0\xadc_wiz_0.xci (and nothing else) in that directory, but removing that file (as the AR suggests) doesn't help. How can I build this example project?
  14. Earlier this year I bought an Arty A7-35T and was able to create a project using Vivado and writing VHDL code. The thing that helped the most to get started was a blinking lights example project. Recently, I bought an Arty Z7-20 board, and would like to use it with SDSoC. I managed to get SDSoC installed and running. Now, how to start writing code? I've spent more than a day looking through various tutorials and getting started guides, but so far haven't found what I really need. One of the most helpful documents I found was the step-by-step "Introduction to the SDSoC Development Environment" at https://www.xilinx.com/html_docs/xilinx2017_4/sdsoc_doc/fzn1504034404694.html or the similar material in the "SDSoC Environment Tutorial Introduction" at https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1028-sdsoc-intro-tutorial.pdf . However, I soon got stuck again when I needed to choose a platform, and Arty Z7 is not in the list of available choices. I found some Arty_Z7_20 platform files at https://github.com/Digilent/SDSoC-platforms and figured out how to add that platform to the list and create a project with that platform. But then the next hurdle is to select the Linux system configuration (it's not available in the Arty_Z7_20 platform) and then, after that, "Select a template to create your project" - there are no templates available in the Arty_Z7_20 platform except "Empty Application". So, how can I proceed? Is there a better getting started guide that I've overlooked, perhaps one that is tailored to the Arty Z7? Is there a blinky light example project that I could build in SDSoC and run on the Arty Z7? If suitable Arty Z7 getting started documentation, platform files, and example projects don't already exist, I'm willing to create them and make them available so the next Arty Z7 user can get started a lot easier. But right now, I need some guidance on how to proceed. Thanks!