Jan Kok

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  1. This post is to report a problem and a workaround. My setup: A few weeks ago I installed Vivado 2016.4 and am using an Arty Z7-20 board. I've been working through the Getting Started with the Vivado IP Integrator tutorial https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. At Section 8.3 where I try to run the demo by clicking Run As > Launch on Hardware (System Debugger), I got "Error while launching program: Memory write error at 0x100000. APB AP transaction error, DAP status f0000021" It turned out that I had the Boot Mode jumper (JP4 on the Arty Z7) set to
  2. Hi @zygot, thanks for sharing your thoughts on this subject. I'm making some progress with getting myblock to work. Now I can connect it, but I'm getting some warnings and errors that I'm trying to resolve. Another approach might be to modify an axi_gpio block, adding my own logic and removing stuff I don't need such as interrupt logic. That would be similar to what you mentioned (creating your own IP), except I would start with known working code rather than developing a new block from scratch. What learning materials did you use to figure out how to make your own IP? I do
  3. Jan Kok


    Indeed! Where do all those numbers that you want to add come from? They probably come from some shared memory or from some input ports. The shared memory or I/O ports are likely to be the main bottleneck limiting your design's performance.
  4. Jan Kok


    In VHDL, "generate" will probably do what you want. Not sure what the equivalent thing is in Verilog.
  5. The connection between axi_gpio_1 and rgb_led is a bundle of 3 busses: gpio2_io_i, gpio2_io_o, and gpio2_io_t. That is revealed by clicking on the "+" sign next to GPIO2 in the block diagram (in my screen shot, the + sign has turned into a - sign). Since GPIO2 is a bundle and inbus is a simple bus, the bus structures don't match, and the block diagram editor won't let me connect them together, and for the same reason won't let me connect outbus with rgb_led. So one question is, how can I make myblock have ports that can be connected with axi_gpio_1 and rgb_led? Another question is, h
  6. I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its
  7. I'm about to install Vivado on a new computer and want to know which version(s) will work for compiling the Arty Z7 and Arty A7 example projects. I'm asking because I've tried to use version 2017.4 twice and had problems each time, possibly due to version incompatibility problems. Using version 2016.4 resulted in success each time. In another thread, @jpeyron said "The xadc project was made for Vivado 2016.4. Unfortunately, the version does matter." Unfortunately, the "Installing Vivado and Digilent Board Files" document https://reference.digilentinc.com/vivado/installing-vivado/star
  8. Hallelujah!!! The XADC demo built and is now running on my Arty Z7-20 board. Thank you, thank you, thank you, @jpeyron !!! The problem was, in the Arty-Z7-20-xadc-2016.4-2.zip (239 KB) file I was using, the repo/Vivado-library folder contained the ip folder only, and that ip folder only had 1.3MB of stuff, when unzipped. The vivado-library-c78277642564934f23b19a086bc575d49653558d that Jon pointed me to (https://github.com/digilent/vivado-library/tree/c78277642564934f23b19a086bc575d49653558d ) is about 170 MB - so a few things were apparently missing from the Arty-Z7-20-xadc-2016.4-2.zip I
  9. "I was describing the window command file cleanup as shown" Yeah, I figured that out eventually :-) So I just created a new work folder c:/Users/janko/Vivado6 and copied Arty-Z7-20-xadc in there, copied all the "new" board files to c:\Xilinx\Vivado\2016.4\data\boards\board_files, then started Vivado 2016.4 and tried to create the project. This is what I got: start_gui cd c:/Users/janko/Vivado6/Arty-Z7-20-xadc/proj/ source ./create_project.tcl # set proj_name "XADC" # if {[info exists ::create_path]} { # set dest_dir $::create_path # } else { # set dest_dir [file norma
  10. Thanks for getting back! "First go to the proj folder and double click cleanup." Um... what file browser should I use to go to the proj folder? I'm asking because I don't see a cleanup button anywhere that I can double click on. Meanwhile, I'll try deleting and reinstalling the xadc demo. I just noticed that I have two identical-looking Vivado 2016.4 icons in my start menu. When I click one of them, I see "Vivado 2016.4" in the title bar. When I click the other one, I see "Vivado 2016.4_sdx" in the title bar. I had been using the sdx one. I'm guessing that was supplied when I install
  11. Any further help with this? As mentioned in my previous post in this thread, I'm still stuck, with both 2016.4 and 2017.4 versions of Vivado. Thanks.
  12. Hi @jpeyron, thanks for reply. In the case of Vivado 2017.4, I did install the arty-z7-20 board files only - not the other board files in the zip file. (Do I need to install the others?) In the case of Vivado 2016.4, I forgot to install the board files. When I looked for them (after writing the note that begins this thread), I was surprised that there was no C:\Xilinx\Vivado\2016.4 directory at all! Though there was a C:\Xilinx\Vivado\2017.4 directory. It was surprising, because there was a Vivado 2016.4 icon in my Start menu (as a result of installing SDSoC 2016.4), and clicking tha
  13. I tried to build the XADC example project using Arty-Z7-20-xadc-2016.4-2.zip , https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-xadc-demo/start , and https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start . Using Vivado 2016.4, after entering the tcl command "source ./create_project.tcl" I get ...# update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2406] Cannot identify part xc7a200tsbg484-1 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJE
  14. Earlier this year I bought an Arty A7-35T and was able to create a project using Vivado and writing VHDL code. The thing that helped the most to get started was a blinking lights example project. Recently, I bought an Arty Z7-20 board, and would like to use it with SDSoC. I managed to get SDSoC installed and running. Now, how to start writing code? I've spent more than a day looking through various tutorials and getting started guides, but so far haven't found what I really need. One of the most helpful documents I found was the step-by-step "Introduction to the SDSoC Development Env