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  1. I'd like to do some measurements without pulling the signal at all. (highest impedance possible to avoid impacting system current)
  2. The one I ordered & received indeed shows RN4871 on the label. To Digilent (sorry to thread-jack): What firmware version is loaded on the modules (this significantly impacts the features) ? Is Data Length Extension supported, and if so to what length (I couldn't find the parameter listed in any of the documentation)?
  3. Also, for step 6, it may be helpful to indicate where to look (upper right corner of the Vivado suite) to see the Bitstream status. I tried to proceed to step 7 when I erroniously though step 6 was done. Hopefully tool revisions don't change the location of the status too much. At least in Vivado 2018.1, the tool has a "Bitstream Generation Completed" pop-up, you might indicate to wait for this with an image of the relevant option {Open Implemented Design, View Reports, Open Hardware Manager, Generate Memory Configurations}to select. I know it's a challenge to keep up with tools that roll frequently. It might help to have a link to a version of Vivado corresponding to the guide, if Xilinx is amenable to that legacy tool link support. Also, to add/clarify to the previous post/question: Including the frame/region any icons or options are located would also help significantly. Coming from an embedded micro-controller background, there interface has many more layers of configuration than code only IDEs. I'm not always clear on which frame/tool to use for this yet.
  4. I'm trying to follow the "Getting started with Zynq" guide to bring up a Zybo board. Step 4.4 indicates "swts_4bits", but the closest option is "sws_4bits". I appreciate the guide immensely, but it might help to also include the icon locations for each step, particularly where the "Add Ip" icon is, since there are a LOT of interface options in Vivado. It may also help to have the steps in hierarchical order, even if it causes the English to be awkward. E.g. instead of "4.3) Select GPIO2 under axi_gpio_0 and select swts_4bits in the drop-down box." something like "Within the block axi_gpio_0 group GPIO2, select sws_4bits" or maybe even axi_gpio_0 -> GPIO2 -> sws_4bits Including the other block configurations (like S_AXI) would also be helpful, even if they're left with their defaults. It looks like Xilinx rolls their tools a lot, so this would help when users are on a different version. I'm new to FPGA/CPLD terms, so please excuse imprecise/wrong term/notation usage. On the other hand, thank you for making such tools so accessible!
  5. I see this page: but the store link goes to a Pmod hat for the Rasperry Pi, and I couldn't find a store page link to buy it. Is it available? -Thanks
  6. In adding support for a Digital Discovery to some scripts I'd made for the Ad2, I noticed that they both report devIDs above the ones listed in the constants file; the AD2 reports a 3 for this, and the DD reports a 4. Can this file be "refreshed" with any missing constants or api changes?
  7. This feature is under the Patterns, Add menu (it took me a little to find it). This looks like it could work. Is there a way to setup this feature using the SDK? Thanks!
  8. I recently purchased a Digital discovery, and the Static IR module made me think that a "crosspoint" feature would be useful for simulating a key matrix (assuming that driving and sensing line do not switch, and that the total propagation delay is low enough). Using a digital crosspoint switch to simulate a key matrix definitely has some differences from the way that a physical matrix behaves (such as noise when the switch opens and closes), but I'd find it useful for developing with, and I think some others would as well. Perhaps more generally, it would be very powerful to be able to do some logic design on board the device, maybe even just macro-cell configuration. Anyway, thanks for quality products and a good (and portable) SDK.
  9. Indeed, I had an off by 1 error. In the 4th mode, FDwfAnalogInStatusSample( ) yields 0 in the voltage parameter for both AD2 Analog In channels.
  10. Thanks for the replies. I am calling the FDwfDeviceConfigOpen function now, but I'm not sure the call is having an impact. Is there a way to verify the setting? In mode 4 (larger Digital buffers, but no analog buffers) will FDwfAnalogInConfigure still return a meaningful result? It would be great if it does, but seeing it return a value makes me think the mode setting didn't work. I am using the Python interface on Ubuntu 14.04 with DWF Version 3.7.5
  11. Thanks for the information @attila What is this 7th configuration? Are the configurations documented somewhere other than the waveform GUI?
  12. Is there any chance there are specs for the VIH and VIL voltage levels in this 1.8V and the 3.3V input mode? It's implied that the pins are still 3.3V tolerant (since some could be setup as outputs), but can you confirm? -Thanks
  13. In the Device manager for the AD2, there's an option for 1V8 Digital inputs. Is there an SDK function equivalent to set/get this, or otherwise adjust to the 1V8 range? Are there specifications on the voltage thresholds (and any other parameters such as setup & hold timing) for both settings? Does using the 1.8V setting impact the 5V tolerance of the pins, or the pin current if > VIO > 3.3V? -Thanks
  14. The power supplies can be controlled under the *AnalogIO* functions (search for "supplies", not "supply"). If you're using the linux command line interface, they are the first 2 channels in the AnalogIO group.