xc6lx45

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  1. Like
    xc6lx45 got a reaction from charlieho in How to connect an external FIFO to FPGA   
    Well, to be honest, I didn't read the datasheet to the high-capacity devices with 9M bits. So this one isn't even EOL.

    Well, it depends.
    Have a look at https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf table 6.
    There are 325 of those 36 kB blocks on the FPGA (11700 kB in total), so you need about 1/4 of the total FPGA for memory.
    Technically feasible and easiest to implement but a very expensive FIFO.

    Now, connecting this chip to realize its full performance potential (e.g. 225 MHz) is not straightforward.

    From between the lines ...
    >> Do I must use all pins of external FIFO?
    ... I read that you don't have hands-on experience with e.g. CMOS ICs (the answer is "you must drive any input at any time, unless the data sheet says explicitly otherwise", or strange things will happen. "Strange" in a sense that the circuit may respond to waving my hands over it, and that's not an exaggeration).
    If I'm correct in this, it may be a good idea to get e.g. a few CD4017 or some other standard CMOS chip with simple functionality for < $1 and use this to bring up your FPGA IOs. If the FIFO chip doesn't work because of IO issues, it will be near-impossible to debug.






  2. Like
    xc6lx45 got a reaction from charlieho in How to connect an external FIFO to FPGA   
    you might give a bit more information to not be mistaken for a lazy student.
    My first thought is simply "do not". The component is EOL and you can have the same using the FPGA's BRAM with a LOT less hassle.
  3. Like
    xc6lx45 got a reaction from Mukul in Dynamic voltage and frequency scaling   
    https://www.xilinx.com/support/documentation/white_papers/wp389_Lowering_Power_at_28nm.pdf page 3
  4. Like
    xc6lx45 got a reaction from Mukul in Dynamic voltage and frequency scaling   
    >> is it possible to present DVFS on it.
    >> For now I now about clock wizard, DCM, PLL for different clock generation (frequency) but this is not frequency scaling mi right?

    you may have your own answer there. This is some university project?

    Have you done your own research? For example, this has all the right keywords:
    https://highlevel-synthesis.com/2017/04/12/voltage-scaling-on-xilinx-zynq


  5. Like
    xc6lx45 got a reaction from aabbas02 in Understand Resource Usage for FIR Compiler   
    Just be aware that most of the "legacy" material on FIR filters limits itself to what can be presented conveniently. Numerical optimization is the tool of choice and there is no "cheating". Or, taking one step back to the filter specs, there is usually no need to specify a flat stopband and it can significantly reduce the required filter size (credits to Prof. Fred Harris) This only as.example where I can avoid unnecessary constraints from using a ready-made design process by writing my own solver. Which is actually not that hard, basing it on fminsolve or fminunc in Matlab / Octave.
    BTW, one reference on this topic I found useful:
     author = {Mathias Lang},
        title = {Algorithms for the Constrained Design of Digital Filters with Arbitrary Magnitude and Phase Responses},
        year = {1999}
    http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.6.9336
    The title alone is interesting - "Arbitrary Magnitude and Phase Responses" - no one says a digital filter needs to be flat or linear phase (of course, at the expense of symmetry).
    Sometimes I wonder, our thinking seems to often get stuck in patterns and "templates". Take analog filters, for example: Chebyshev, Butterworth or Bessel, which one do I pick? But those are just corners of the design space, and the best filter for a given application is most likely somewhere in-between, if I can only design it (which is, again, a job for a numerical optimizer, even though this one is more difficult).
     
  6. Like
    xc6lx45 got a reaction from aabbas02 in Understand Resource Usage for FIR Compiler   
    The word "overclocking" may be even misleading - this architecture is used when the data rate is significantly lower than the multiplier's speed.
    Inputs to one (expensive) multiplier are multiplexed, so it can do the work for several or all taps. The "multiplexing" itself will get fairly expensive in logic fabric due to the number of data bits and coefficients. To the rescue comes the BRAM, which is essentially a giant demultiplexer-multiplexer combo, with a football field of flipflops in-between.
    You can find an example for this approach here. Out-of-the-box, it's unfortunately quite complicated because it does arbitrary rational resampling. Setting the rates equal for a standard FIR filter, you end up with only a few lines of remaining code.
    BTW, multiplier count as design metric is probably overrated nowadays for several reasons (the IP tool resource usage is already more practical, e.g. BRAM count may become the bottleneck).
    If you can get this book through your library, you might have a look e.g. at chapter 6 (background only, this is a very old book):
    Keshab K. Parhi VLSI Digital Signal Processing Systems: Design and Implementation
  7. Like
    xc6lx45 got a reaction from aabbas02 in Understand Resource Usage for FIR Compiler   
    Hi,
    [1 2 3 4 0 1 2 3 4] is not symmetric in a linear-phase sense. That would be e.g. [1 2 3 4 0 4 3 2 1]. You could exploit the shared coefficients manually, see e.g. Figure 3 for the general concept. But this case is so unusual that I doubt tools will take it into account.
    The tool does nothing magical. If performance matters more than design time, you'll always get better results for one specific problem with manual design. One performance metric is multiplier utilization (e.g. assuming you design for a 200 MHz clock, one DSP delivering 200M operations / second performs at 100 %. Reaching 50+ % is a realistic goal for a simple / single rate structure).
    For example, do I want to use an expensive BRAM at all, when I could use ring shift registers for delay line and coefficients. Then you only need a small controlling state machine around it that does a full circular shift for each sample, muxing in the new input sample every full cycle (the BRAM makes more sense when the filter serves many channels in parallel, then FF count becomes an issue).
  8. Like
    xc6lx45 got a reaction from grf in Defective JTAG on Digilent Cmod A7-35T board   
    if you can bring it up once in Vivado HW manager (maybe with the help of an external +5 V supply), you might be able to erase the flash.
    If not, you may be able to prevent loading the bitstream from flash e.g. by pulling INIT_B low (R32 is on the bottom of the board, its label slightly below the CE mark). See https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf "INIT_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process. When a High is detected at the INIT_B input after the initialization process, the FPGA proceeds with the remainder of the configuration sequence dictated by the M[2:0] pin settings.""
  9. Like
    xc6lx45 got a reaction from Ahmed Alfadhel in Visualizing 5 kHz sine wave by Pmod DA3   
    well, by default your signal is between 0 V and Vref. The opamp circuit has a gain of 2 (range 0.. 2 VRef) but subtracts a constant VRef (range now -VRef..Vref).
    It'll just shift the waveform on the scope, and double its AC magnitude.
     
  10. Like
    xc6lx45 got a reaction from jpeyron in How to replace the function of "adept 2"?   
    Hi,
    I think a UART is the least effort. Parsing ASCII hex data in a state machine is easy and intuitive to debug, at the price of 50 % throughput.
    If you like, you can have a look at my busbridge3 project here, goes up to 30 MBit/second. The example RTL includes very simple bus logic with a few registers, so it's fairly easy to connect an own design. Note, it's not meant for AXI, microblaze or the like as it occupies the USB end of the JTAG port.
    In theory, it should work on any Artix & FTDI board as it doesn't any LOC-constrained pins.
  11. Like
    xc6lx45 got a reaction from TerryS in Vivado free for Artix-7?   
    Just as a reality check: To e.g. make a LED blink, the required CMOD A7-specific content is about five lines of constraints from CMODA7_Master.xdc. This may look more complicated than it actually is. And BTW, good choice, it's a great little board 🙂
  12. Like
    xc6lx45 got a reaction from Jaraqui Peixe in XPS license for ISE 14.7 System Edition Request   
    Hi,
    >> We are forced to work in assembly with picoblaze.
    you might have a look at the ZPU softcore CPU with GCC. The CPU is just a few hundred lines of code but most of its functionality is in software in the crt.o library in RAM. I understand it's quite well tested and has been used in commercial products.
    Not surprisingly, using an FPGA to implement a processor that then kinda emulates itself in software (aka RISC :) ) is maybe not the most efficient use of silicon - I'm sure it has many strong points but speed is not among them...
    Unfortunately, the broken-ness of Xilinx' DATA2MEM utility (to update the bitstream with a new .elf file) spoils the fun, at least when I tried in ISE14.7 (segfaults). When it works, the compile/build cycle takes only a second or two.
    Long-term, porting the processor to a new platform would be straightforward, or even fully transparent if using inferred, device-independent memory. This would also work for a bootloader that is hardcoded into default content in inferred RAM. I might consider this myself as a barebone "hackable" CPU platform strictly for educational purposes.
  13. Like
    xc6lx45 got a reaction from jpeyron in Nexys 4 DDR - Read signals from photodiode reciver   
    Hi,
    >> applying various algorithms
    if you don't know the algorithms yet, it might be easier to get the ADC data into a softcore CPU, then prototype in C using floating point. The point is, experimental prototyping of algorithms in fixed point RTL is a slow and painful process.whereas reloading a .elf binary takes a second.
    I'm guessing your intent but I suspect you'll find eventually that an FPGA is not the optimal platform choice for your application. Meaning, you can most likely get the same result cheaper and with less effort e.g. using a Raspberry PI + SPI converter. I'm guessing this simply because higher-rate ADCs where FPGA makes sense (hundreds of MHz) are hard to come by as OTS modules. Otherwise, if you design for, say, 1 MSPS, the FPGA fabric will do less than 1 % of the work it could do but you pay for 100 % so people usually don't use FPGA, if a CPU or DSP will do the job.
  14. Like
    xc6lx45 got a reaction from Jonathon Kay in Would I be able to self learn FPGA programming Zynq 7000 series?   
    Hi,
    there's a lot of new information in your last post. You aren't just "trying" FPGA but have a professional interest in Zynq.
    Don't let anybody scare you it's "difficult" and go for it, possibly with the cheapest board, no tutorials and low expectations like, blinking LEDs for quite a while.
    Given the price tag of any industrial training coarse, an FPGA board for self-study is a no-brainer.
    Maybe save some money to buy your FPGA engineer a coffee once a week, with some questions in mind
     
  15. Like
    xc6lx45 got a reaction from [email protected] in Would I be able to self learn FPGA programming Zynq 7000 series?   
    Hi,
    there's a lot of new information in your last post. You aren't just "trying" FPGA but have a professional interest in Zynq.
    Don't let anybody scare you it's "difficult" and go for it, possibly with the cheapest board, no tutorials and low expectations like, blinking LEDs for quite a while.
    Given the price tag of any industrial training coarse, an FPGA board for self-study is a no-brainer.
    Maybe save some money to buy your FPGA engineer a coffee once a week, with some questions in mind
     
  16. Like
    xc6lx45 got a reaction from [email protected] in Green/Red detector and button controlled car (BASYS3/VHDL)   
    Hi,
    >> I would be really glad if someone helps 
    no one is going to do your course homework for you. But, I think you should talk with your supervisor. You've been thrown in at the deep end of the pool, which is OK only for someone who knows how to swim. Reading between the lines, you don't.
    Now if this is a follow-up to a VHDL course: Review the course material and lab exercises, it will probably give you some shortcuts. If one could teach simply by throwing people into the pool, there would be no need for schools...
    Otherwise, it looks (based on your post, of course), like a nasty amount of work without any focus e.g. connecting to "a" toy RC car feels like an exercise in tinkering, not engineering e.g. buy a $10 RC toy and hack the transmitter with an MTC61-ish optocoupler. To the FPGA, it looks like a LED.
    Do not assume it's easy (in a sense of "don't assume swimming is easy").
  17. Like
    xc6lx45 got a reaction from [email protected] in Would I be able to self learn FPGA programming Zynq 7000 series?   
    >> But it will cost me a bomb and I need to be sure I am investing on the correct thing.
    My entry for the "shortest answer" competition:
    Get a CMOD A7 or similar. It's dirt cheap - consider it disposable and save the idea of buying something "more capable" for long term motivation. Starting with an expensive board, then being afraid to use it for fear of breaking it does not help with learning.
    Zynq is significantly more complex than Artix and the FPGA part is less accessible.
  18. Like
    xc6lx45 got a reaction from jpeyron in Zybo Z7 Board Using Raspberry Pi Camera Module V2-8 Megapixel,1080p   
    You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.
  19. Like
    xc6lx45 got a reaction from enriqeat in Different current flow on 2 output pins of JE standar Pmod port   
    Hi,
    >> I understand the if the pin is an output, then current should exit from it
    Most likely, your understanding of the output cell is wrong.The point is the "C" in CMOS, "complementary". Look at the first picture in the link - there are two (MOS) transistors, one to positive supply voltage and one to negative / GND. The pin can source and sink current. This is the magic behind almost all  modern digital circuitry.
    And if anybody wonders what would happen if both switches would open at the same time. Magic smoke appears  🙂
  20. Like
    xc6lx45 got a reaction from Ahmed Alfadhel in How to visualize clock signal of ARTY 7 kit using oscilloscope?   
    and are you using the probe in x10 mode?
  21. Like
    xc6lx45 got a reaction from Ahmed Alfadhel in How to visualize clock signal of ARTY 7 kit using oscilloscope?   
    are you maybe using a low-speed analog output with 200 ohms series resistor?
    Check the schematic of the board for a direct output.
     
  22. Like
    xc6lx45 got a reaction from TireV in Cmod S6 - Multilayer?   
    You might go to Texas Instruments' site (or AD or both) and find documentation for some $500 high frequency ADC or DAC eval board as example to study..
    There's nothing wrong with copper planes, generally. Free-standing structures (such as non-connected filler polygons) can be bad, if they resonate. So are loops if the driving wire spans an area together with the GND return wire (for which the ground plane is an obvious solution).
    The worst resonators have high quality factor meaning loose coupling meaning it can be surprising how the energy managed to couple in. There's no such thing as too many ground vias...
    Note, your ground plane can do very interesting things in combination with the metal box it's in (resonant cavity) but that's a different story.
     
  23. Like
    xc6lx45 got a reaction from jpeyron in Cmod S6 - Multilayer?   
    You might go to Texas Instruments' site (or AD or both) and find documentation for some $500 high frequency ADC or DAC eval board as example to study..
    There's nothing wrong with copper planes, generally. Free-standing structures (such as non-connected filler polygons) can be bad, if they resonate. So are loops if the driving wire spans an area together with the GND return wire (for which the ground plane is an obvious solution).
    The worst resonators have high quality factor meaning loose coupling meaning it can be surprising how the energy managed to couple in. There's no such thing as too many ground vias...
    Note, your ground plane can do very interesting things in combination with the metal box it's in (resonant cavity) but that's a different story.
     
  24. Like
    xc6lx45 got a reaction from jpeyron in busbridge3: High-speed FTDI/FPGA interface   
    laughing out loud ... Formula-1-performance is niche business, combine harvesters bring home the money, walking barefoot is the norm.
    And why not, I'm even discouraging people to touch it as long as a UART does the job. Same as with fast cars, speed is largely overrated. Those who know otherwise, you know who you are 🙂
  25. Like
    xc6lx45 reacted to hamster in Number of LUT in xc7a35ticpg236-1L Artix-7   
    You are not wrong - but for that device ID the tooling will not let you use all the LUTs present on the silicon die.
    It is a somewhat artificial restriction, and might have some implications for the power and thermal properties of the package (e.g. a smaller package may not be able to dissipate the heat).