xc6lx45

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Posts posted by xc6lx45


  1. 11 hours ago, RFtmi said:

    128 digitized data outputs about 4Mbps each.

    isn't that 512 Mbps, with USB 2.0 ~ 480 Mbps max? And I wouldn't bet on achieving that.

    You could set up a simple Ethernet UDP dummy data generator on Zynq with what would be a few lines of C code on regular Linux, to check how much of that "gigabit" is actually achievable. But I suspect your requirements are deep in PCI territory.

    BTW, I'm still looking for the 128 IOs on this board.

     


  2. 2 hours ago, RFtmi said:

    I want to use the Cora board to combined multiple low data rate signals and send it through the USB 2.0 port to a computer. I need the full speed of the USB 2.0. Do I need to buy a license for USB 2.0 from Xilinx to use Vivado for programming it? Is there any example code for running the USB 2.0 you could refer me to?

    Reading between the lines (apologies if I'm wrong, this is based solely on four sentences you wrote so prove me wrong): I see someone ("need the full speed ...") who'll have a hard time in embedded / FPGA land. For example, what is supposed to sit on the other end of the cable? A driver, yes, but for what protocol and where does that come from?

    Have you considered Ethernet? It's relatively straightforward for passing generic data and you could use multiple ports for different signals to keep the software simple. UDP is less complex than TCP/IP and will drop excess data (which may be what I want, e.g. when single-stepping code on the other end with a debugger).


  3. Hi,

    when you load a Zynq bitstream from Vivado there are a few things that happen "automagically", like powering up the level shifters on the PS-PL interface (clock!). Zynq doesn't support FPGA-only operation, but you can manage with an autogenerated "FSBL" (first stage boot loader).

    Vivado, "export hardware" and include bitstream checked.

    Then you need to open SDK ("File/launch SDK") and create a "FSBL" project. Compiling it results in a .elf file. Put this into a boot image (.bin or .mcs) at the first position, the FPGA bitstream on position 2. Flash the result and the FPGA image will load at powerup when QSPI mode is jumpered.

    Note, the SDK flash utility does not work reliably (sometimes fails with error) when Vivado is still connected to the hardware.

    I'm sure there are tutorials but this as a two-line answer.

     

     


  4. You could use the multiplication operator "*" in Verilog (similar VHDL).

    For example, scale the "mark" sections (level 10) by 1024, the "space" sections (level 3) by 307. This will increase the bit width from 12 to 22 bits, therefore discard the lowest 10 bits and you are back at 12 bits. Pay attention to "signed" signals at input and output, otherwise the result will be garbled.


  5. Hi,

    could this be a signed-/unsigned issue?

    BTW, once you've got it working, for XADC rates (up to 1 MSPS) "systolic" architecture using 45 DSP slices seems overkill. It can probably be done in one slice (you need 89 MMAC/s/channel, it's not hard to clock a DSP slice at 200 MHz).

    And, the XADC actually outputs 16 bits. The lowest 4 bits are not specified e.g. no guarantees for no missing codes etc but useful in average. I would probably use them. Otherwise, for a non-dithered ADC, the quantization error becomes highly correlated with the input signal at low levels and causes weird artifacts.


  6. On 8/6/2019 at 2:53 PM, tdavismn said:

    where I can get reported the rms voltage value over frequency

    Hi,

    a conventional spectrum analyzer shows average power observed within the resolution bandwidth (RBW) filter. I need a correction factor from the RBW filter to the equivalent noise bandwidth of the filter, either from the analyzer's manual or via the analyzer's firmware (e.g. 'noise density' marker or the like that performs the conversion automatically). I can ignore this factor but it won't be fully accurate then. The difference is between definitions e.g. -3 dB bandwidth vs. an equivalent brickwall filter with the same area under the curve.

    For a "raw" FFT-based spectrum analyzer, the RBW is about the inverse of the capture time, e.g. 1 ms capture = 1 kHz RBW.

    Knowing power in RBW, I scale down to power in 1 Hz. E.g. with a 300 kHz RBW (noise) bandwidth, divide the power (in units of Watts) by 300000.

    Then convert to voltage over 50 ohms and there is the RMS value (since spectrum analyzer power readings mean "dissipated over the SA's 50 ohms input resistance).

    This for the vendor-independent basics...


  7. is it possible that you simply need to right-click the ports, "make external" or the like?


  8. On 8/2/2019 at 2:28 AM, sungsik said:


    So i think it can be done by using xilinx library in SDK . Is there any better method?

    Question is, what's "better". If I'd use standard AXI blocks and SDK, the motivation would be that other people can work easily with the design, using the higher-level description. This would be my strong preference. Also, that you can have working code within about 60 seconds.

    If your project is large enough to warrant a more "efficient" implementation (keeping in mind that Xilinx is motivated to sell silicon by the square meter, not to use it at maximum efficiency), a custom RTL blocks and direct access via volatile unsigned int pointers. But for "controlling it via a PC" this is simply not relevant.

     


  9. On 8/1/2019 at 11:56 PM, hamster said:

    Using a tool for what it is meant to do is easy. Using a tool for something where it isn't suited, that is where the learning begins!

    That's the spirit :)

    I'm just commenting because Hilbert transform looks like a wonderful tool for its conceptual simplicity. And textbooks get carried away on it. And of course it does have valid technical applications. But it can easily turn into the steamroller approach to making apple puree, and DSP tends to become unforgiving a few minutes into the game when "implementation effort" plays against "signal quality" on linear vs logarithmic scales.

    At the end of the day, it boils down to the same idea - elimination of the negative frequencies so cos(omega t) = 1/2 (exp(- i omega t) + exp(i omega t)) becomes constant-envelope exp(i omega t)


  10. 22 hours ago, hamster said:

    Going to Incorporate it into my (MCU based) guitar tuner... but it is a nice tool to have in the kit.

    But this would an example where it's trivially easy to generate the reference tone in quadrature. Multiply with the complex-valued reference tone, lowpass-filter to suppress the shifted negative frequency component and there's my analytical ("one-sided spectrum") signal for polar processing.

    Now to be honest I've never ever designed a guitar tuner but I suspect that this with a decimating lowpass filter (no point in maintaining an output rate much higher than the filter bandwidth) can be orders of magnitude cheaper because I'm designing for the tuner's capture bandwidth (say, 10 % of the high E string fundamental would be ~30 Hz) instead of audio frequency.

     


  11. 4 hours ago, D@n said:

    Verilator ... The disadvantage is that the simulation is all clock based.  You lose the fractional clock resolution.  For me, this has been good enough.

    enter VHDL-AMS and spend coffee breaks reminiscing about the days when simulation "was" all clock based... Adaptive time step control... works for differential equations so it'll sure work for digital systems, too... strictly monotonic time was yesterday... umm, which 'yesterday', the one we just had or the one that hasn't happened yet...

    Oh well, I digress...


  12. I'd recommend you spend a working week "researching" the electrical-engineering aspects.

    The ADC may look just as an afterthought to DSP but it will require significant engineering resources (plan for several / many man-months). Long is the list of bright-eyed students / researchers / engineers / managers who have learned the hard way that there is a bit more to the problem than finding two boards with the same connector...

    Hint, check how much latency you can tolerate and research "digitizer" cards for PC (or PXI platform). If you don't need a closed-loop real-time system, don't design for a closed-loop realtime system.


  13. On 7/25/2019 at 11:13 AM, hamster said:

     it looks like you just need to apply a low-pass filter

    yes, for an application with basic requirements, like receiver gain control this will probably work just fine (it's equivalent to an analog envelope detector). Now it needs a fairly high bandwidth margin between the modulation and the carrier, and that may make it problematic in more sophisticated DSP applications (say "polar" signal processing when I try to reconstruct the signal from the envelope) where the tolerable noise level is orders of magnitude lower.

     

     


  14. Hi,

    you can get a permanent webpack license straight from Xilinx within a minute. You need the same registration info that was used to download Vivado.


  15. Well yes and no. The question I'd ask is, can you use a local oscillator somewhere in your signal path with a 90 degree offset replica. In many cases this is trivially easy ("trivially" because I can e.g. divide digitally from double frequency or somewhat less trivially, use, say, a polyphase filter. In any way, it's probably easier on the LO than on the information signal because it's a single discrete frequency at a time, where the Hilbert transform approach needs to deal with the information signal bandwidth).

    If so, downconvert with sine and cosine ("direct conversion") and the result will be just the same. After lowpass filtering, square, add, take square-root, there's your envelope . When throughput / cost matters (think "Envelope tracking" on cellphones) it is not uncommon to design RTL in square-of-envelope units to avoid the square root operation. Or if accuracy is not that critical, consider a nonlinear bit level approximation see "root of less evil, R. Lyons".

    Of course, Hilbert transform is a viable alternative, just a FIR filter (if complex-valued).

    In case you can't tell the answer right away, I recommend you do the experiment in the design tools what happens if you try to reach 0 Hz (hint, "Time-bandwidth product, Mr. Heisenberg". Eventually it boils down to fractional bandwidth and phase-shifting DC remains an unsolved problem...).

     

     


  16. Quick answer: JTAG is included. The USB cable is all you need (but get a quality "mini" size cable. Bad cables cause probably the most problems with this board).

    edit: MICRO USB cable, not mini...


  17. maybe I'm bone-headed but "I used the Xilinx wizard to generate an AXI-Lite template. I edited a few lines and it worked right away" would be my recommended answer for an "industrial" job interview :)

     


  18. well, what can I say...
    It's the official flow so I'd start under the assumption that it works as expected.

    The last time I tried a generated 4-register 32-bit AXI-Lite slave, it did work as expected.


  19. Actually, Xilinx makes this easy. You don't need to do all the groundwork by yourself, and the result is plain HDL (no encrypted "wizardry" or the like, just a plain HDL file for you to edit).

    Main menu: Tools / create and package new IP / select create new AXI peripheral. Edit names, and note the "interface type" combo box that should be set to "Lite".

    Create e.g. 4 32-bit registers to start with. The resulting HDL is pretty straightforward.


  20. PS: I'm not sure whether FS_CLK is up when you upload the bitstream from Vivado. It originates from the processor subsystem, which is brought up by the FSBL bootloader.

    I can't recall how the tools handle it I wouldn't be surprised if there is no clock for bitstream-only operation.

     


  21. >> But I think that I could use two edges

    as was already said above - even if the language can express this seamlessly, it doesn't make sense for the hardware you're working with.

    The language is more flexible than the FPGA, for simulations / testbenches / historical reasons. And note, if your course wasn't FPGA-specific, ASICs are again more flexible than FPGAs.

    Note also that sadly, many courses turn out to be effectively "simulation only", possibly taught by people lacking hands-on experience beyond the simulator. It doesn't hurt to review any known concept critically, "does this really apply to FPGA"...