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Everything posted by xc6lx45

  1. You could use the multiplication operator "*" in Verilog (similar VHDL). For example, scale the "mark" sections (level 10) by 1024, the "space" sections (level 3) by 307. This will increase the bit width from 12 to 22 bits, therefore discard the lowest 10 bits and you are back at 12 bits. Pay attention to "signed" signals at input and output, otherwise the result will be garbled.
  2. Hi, could this be a signed-/unsigned issue? BTW, once you've got it working, for XADC rates (up to 1 MSPS) "systolic" architecture using 45 DSP slices seems overkill. It can probably be done in one slice (you need 89 MMAC/s/channel, it's not hard to clock a DSP slice at 200 MHz). And, the XADC actually outputs 16 bits. The lowest 4 bits are not specified e.g. no guarantees for no missing codes etc but useful in average. I would probably use them. Otherwise, for a non-dithered ADC, the quantization error becomes highly correlated with the input signal at low levels and causes weird artifacts.
  3. Hi, a conventional spectrum analyzer shows average power observed within the resolution bandwidth (RBW) filter. I need a correction factor from the RBW filter to the equivalent noise bandwidth of the filter, either from the analyzer's manual or via the analyzer's firmware (e.g. 'noise density' marker or the like that performs the conversion automatically). I can ignore this factor but it won't be fully accurate then. The difference is between definitions e.g. -3 dB bandwidth vs. an equivalent brickwall filter with the same area under the curve. For a "raw" FFT-based spectrum analyzer, the RBW is about the inverse of the capture time, e.g. 1 ms capture = 1 kHz RBW. Knowing power in RBW, I scale down to power in 1 Hz. E.g. with a 300 kHz RBW (noise) bandwidth, divide the power (in units of Watts) by 300000. Then convert to voltage over 50 ohms and there is the RMS value (since spectrum analyzer power readings mean "dissipated over the SA's 50 ohms input resistance). This for the vendor-independent basics...
  4. xc6lx45

    Custom IP

    is it possible that you simply need to right-click the ports, "make external" or the like?
  5. Question is, what's "better". If I'd use standard AXI blocks and SDK, the motivation would be that other people can work easily with the design, using the higher-level description. This would be my strong preference. Also, that you can have working code within about 60 seconds. If your project is large enough to warrant a more "efficient" implementation (keeping in mind that Xilinx is motivated to sell silicon by the square meter, not to use it at maximum efficiency), a custom RTL blocks and direct access via volatile unsigned int pointers. But for "controlling it via a PC" this is simply not relevant.
  6. That's the spirit I'm just commenting because Hilbert transform looks like a wonderful tool for its conceptual simplicity. And textbooks get carried away on it. And of course it does have valid technical applications. But it can easily turn into the steamroller approach to making apple puree, and DSP tends to become unforgiving a few minutes into the game when "implementation effort" plays against "signal quality" on linear vs logarithmic scales. At the end of the day, it boils down to the same idea - elimination of the negative frequencies so cos(omega t) = 1/2 (exp(- i omega t) + exp(i omega t)) becomes constant-envelope exp(i omega t)
  7. But this would an example where it's trivially easy to generate the reference tone in quadrature. Multiply with the complex-valued reference tone, lowpass-filter to suppress the shifted negative frequency component and there's my analytical ("one-sided spectrum") signal for polar processing. Now to be honest I've never ever designed a guitar tuner but I suspect that this with a decimating lowpass filter (no point in maintaining an output rate much higher than the filter bandwidth) can be orders of magnitude cheaper because I'm designing for the tuner's capture bandwidth (say, 10 % of the high E string fundamental would be ~30 Hz) instead of audio frequency.
  8. enter VHDL-AMS and spend coffee breaks reminiscing about the days when simulation "was" all clock based... Adaptive time step control... works for differential equations so it'll sure work for digital systems, too... strictly monotonic time was yesterday... umm, which 'yesterday', the one we just had or the one that hasn't happened yet... Oh well, I digress...
  9. xc6lx45


    I'd recommend you spend a working week "researching" the electrical-engineering aspects. The ADC may look just as an afterthought to DSP but it will require significant engineering resources (plan for several / many man-months). Long is the list of bright-eyed students / researchers / engineers / managers who have learned the hard way that there is a bit more to the problem than finding two boards with the same connector... Hint, check how much latency you can tolerate and research "digitizer" cards for PC (or PXI platform). If you don't need a closed-loop real-time system, don't design for a closed-loop realtime system.
  10. stating something that may be very obvious (or not): You don't need a GPIO IP to drive IO pins. If you have your own RTL block already, it's a three line job in Verilog / VHDL.
  11. search this forum for "ADC eval board". You'll find a lot of material to read. The problem is most likely more difficult than you'd like.
  12. yes, for an application with basic requirements, like receiver gain control this will probably work just fine (it's equivalent to an analog envelope detector). Now it needs a fairly high bandwidth margin between the modulation and the carrier, and that may make it problematic in more sophisticated DSP applications (say "polar" signal processing when I try to reconstruct the signal from the envelope) where the tolerable noise level is orders of magnitude lower.
  13. Hi, you can get a permanent webpack license straight from Xilinx within a minute. You need the same registration info that was used to download Vivado.
  14. Well yes and no. The question I'd ask is, can you use a local oscillator somewhere in your signal path with a 90 degree offset replica. In many cases this is trivially easy ("trivially" because I can e.g. divide digitally from double frequency or somewhat less trivially, use, say, a polyphase filter. In any way, it's probably easier on the LO than on the information signal because it's a single discrete frequency at a time, where the Hilbert transform approach needs to deal with the information signal bandwidth). If so, downconvert with sine and cosine ("direct conversion") and the result will be just the same. After lowpass filtering, square, add, take square-root, there's your envelope . When throughput / cost matters (think "Envelope tracking" on cellphones) it is not uncommon to design RTL in square-of-envelope units to avoid the square root operation. Or if accuracy is not that critical, consider a nonlinear bit level approximation see "root of less evil, R. Lyons". Of course, Hilbert transform is a viable alternative, just a FIR filter (if complex-valued). In case you can't tell the answer right away, I recommend you do the experiment in the design tools what happens if you try to reach 0 Hz (hint, "Time-bandwidth product, Mr. Heisenberg". Eventually it boils down to fractional bandwidth and phase-shifting DC remains an unsolved problem...).
  15. Quick answer: JTAG is included. The USB cable is all you need (but get a quality "mini" size cable. Bad cables cause probably the most problems with this board). edit: MICRO USB cable, not mini...
  16. xc6lx45

    Beyond Hello World

    maybe I'm bone-headed but "I used the Xilinx wizard to generate an AXI-Lite template. I edited a few lines and it worked right away" would be my recommended answer for an "industrial" job interview
  17. xc6lx45

    Beyond Hello World

    well, what can I say... It's the official flow so I'd start under the assumption that it works as expected. The last time I tried a generated 4-register 32-bit AXI-Lite slave, it did work as expected.
  18. xc6lx45

    Beyond Hello World

    Actually, Xilinx makes this easy. You don't need to do all the groundwork by yourself, and the result is plain HDL (no encrypted "wizardry" or the like, just a plain HDL file for you to edit). Main menu: Tools / create and package new IP / select create new AXI peripheral. Edit names, and note the "interface type" combo box that should be set to "Lite". Create e.g. 4 32-bit registers to start with. The resulting HDL is pretty straightforward.
  19. reading between the lines, I think it's unlikely you have a suitable problem for this solution ("analog" delay is a fairly specialized feature). How about a shift register or even a counter?
  20. check LUTs and FFs... implementation removes your whole design, more or less. For example, accidentally not driving a clock can cause this.
  21. PS: I'm not sure whether FS_CLK is up when you upload the bitstream from Vivado. It originates from the processor subsystem, which is brought up by the FSBL bootloader. I can't recall how the tools handle it I wouldn't be surprised if there is no clock for bitstream-only operation.
  22. >> But I think that I could use two edges as was already said above - even if the language can express this seamlessly, it doesn't make sense for the hardware you're working with. The language is more flexible than the FPGA, for simulations / testbenches / historical reasons. And note, if your course wasn't FPGA-specific, ASICs are again more flexible than FPGAs. Note also that sadly, many courses turn out to be effectively "simulation only", possibly taught by people lacking hands-on experience beyond the simulator. It doesn't hurt to review any known concept critically, "does this really apply to FPGA"...
  23. xc6lx45

    Problem with CMOD A7

    This board is fairly demanding when it comes to cables. It's very common with FPGA boards that some cable works with device x but not device y (there are many low-quality cables on the market and they fail gradually). I'd suggest to get a new, quality one. It seems cheap advice but if the cable is the root cause, it needs to be fixed there.
  24. Nothing to worry about if only one is up at a time. It would mean that the frequencies of adjacent oscillators affect each other if they are running at the same time ("injection pulling", to the point that they agree on a common frequency ("locking"). Consider the oscillator as an amplifier with a feedback loop. The feedback path plus phase shift lead to a fairly narrow frequency response around the oscillation frequency or harmonically related frequencies). Weird things can happen with the gain - while it is unity in average steady-state operation, the circuit can get highly sensitive to external interference that is (near)-correlated with the oscillator's own signal. Wikipedia: Perhaps the first to document these effects was Christiaan Huygens, the inventor of the pendulum clock, who was surprised to note that two pendulum clocks which normally would keep slightly different time nonetheless became perfectly synchronized when hung from a common beam
  25. BTW do you have several oscillators up at the same time, or only one? (risk of injection locking) I think RC time constant charging is the most likely reason for the differences. It may well be that the wires at the edge drive fewer (transmission) gates, less capacitive loading, smaller RC and thus faster. But who knows what micro-optimizations e.g. transistor size are involved (maybe also to save power). You might get an insight into what the tool knows if you check the predicted path delay between identical nodes in different rows. It'll also show the logic delay separately so you can check whether LUTs in different locations are known to the tool to have different speed.