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Everything posted by xc6lx45

  1. >> Could I instantiate 1024 blocks so that the samples of the resulting array could be calculated concurrently? It does not seem a likely design pattern. Before you try, sketch out the the resource usage. More likely, you'd implement a single block that gives one sample per clock cycle and run it at 1024 times the frequency, then mux the outputs. For example, assume the samples are for audio at 48 kHz, you'd need 48000*1024 = 49.152 MHz minimum, which is not much for an FPGA
  2. Hi, for a DA converter hack, you could also have a look at the one I used here: There was quite a bit of discussion about reconstruction filtering . The shown measurements are taken using the on-board XADC, which acts as lowpass filter. I think the first two plot labels are wrong (plot 1, 2 show a sine wave. Plot 3, 4 show an 8-tone test signal) It's not sigma-delta but open-loop PWM with creative dithering. The idea is - I generate a PWM signal simply by comparing the output value MSBs against a periodic ramp (e.g. 4 bit) - for the lower bits, use pseudorandom numbers It modulates most of the quantization error up to higher frequencies, where it can be filtered by analog means. Sigma-Delta is more sophisticated (this one might be 8..10 bit equivalent for an audio signal). The main advantage of the PWM scheme is that it works rail-to-rail, where sigma-delta does not. Missing above: "outputBitReg <= myDacVal >= pwm; Note that it's feedforward-only so it should be clocked fairly high e.g. 250 MHz on Artix. The code allows also a 5-bit ramp but I got best results using 4 bits (if in doubt, experiment - depends on the lowpass).
  3. Hi, >> but I feel like lost in documents Welcome to FPGAs. This is pretty much the name of the game (but it also makes the struggle worthwhile - if it were easy, everybody would do it šŸ™‚ ). As a general direction, a solid (basic) tutorial is good but don't expect to be led by the hand all the way. The constant version changes make this quite difficult (good news: it means there is technological progress ... well at least in theory but the guys from the marketing department said so and they'll surely know ...). More specific directions: Have a look at Microblaze MCS. It's fairly simple - set up the most basic system with some BRAM (=memory "internal" to the FPGA fabric) and one UART. Once you've got that printing "Hello World" - which is mostly a question of baud rates and not mixing Tx/Rx pins, you can add features one by one and the sky is the limit. Well, at least until the little girl next door pulls out her Raspberry Pi, running four cores at 10x the clock frequency - don't complain no one told you: by absolute standards, the performance of any softcore CPU is pathetic, compared to a regular ASIC CPU on the same technology node. So eventually you'll have to move into FPGA territory, or it makes little sense except as a learning exercise.
  4. BTW a reliable decoding / recoding UART repeater is conceptually harder than you'd think: UART has a fairly high (percent range) tolerance for timing mismatch. If your source clock is slightly fast and data is uninterrupted, the repeater will eventually be forced to drop bytes.
  5. Hi, as a simple (oversimplified?) answer, designing for higher clock speed requires higher effort (possibly "much" higher effort), and the resulting optimizations make the code harder to work with. Using the clocking wizard to generate a 500 MHz PLL is easy (try it). But writing logic at those frequencies is a different story (e.g. try to implement a conventional counter that divides down to 1 Hz. Why do all those XYX_CARRY signals show up in the timing report already at synthesis?). You also need to distinguish between what is feasible in plain logic fabric, and what can be done with dedicated "hard-macro" IP blocks such as SERDES.
  6. well, don't bother with PXI. It's industrial stuff but cost is 10x off. Check for something that works with minor adjustments. The amateur radio folks are really good at coming up with low-cost solutions, but often there's a crazy amount of work and high level of expertise that goes into it. >> Iā€™m not a programmer Stay away from FPGA šŸ™‚ At least, do your homework before you start buying gear that "should'" do the right thing.
  7. Hi, >> Want use Digilent modules for A plug and play SDR. you can probably find an ADC board that meets your specs but that leaves you with unsolved problems a) SDR b) plug-and-play and c) radio issues that are beyond software, e.g. interferers as below. From between the lines I read that you're not majoring in radio / communications engineering, and probably are not inclined to learn it all the hard way on your "plug-and-play" project... A more practical approach might be to find a similar application and check, what equipment they use. Do you have any clue about the interferers that will be present? 1/2 f, 1/3 f, combinations of a*f1 + b*f2 = f ? Strong blockers in your band of interest? The sensitivity will most likely be useless unless you have solved all the problems in this chapter. If I had to whip up something quickly (but not for pennies), I'd start with PXI cards, some minicircuits LNA, most likely some external filter. The "plug-and-play" SDR continues then from the IQ data.
  8. I can only speak for myself but I'm wondering whether openly asking other people to do your homework problem is accepted use of this forum.
  9. OK I think there's quite a bit lost in translation. Yes, PLL (/MMCM) are the conventional way to go, via the clocking wizard.
  10. is this a homework problem?
  11. I suspect the AD2 with 100 MHz converters won't be much help but actually this nanovna you mentioned looks cool. Thanks for the link, I think I'll get one for my lab coat pocket (note, this one is designed as VNA and does have a RF frontend with synthesizers and mixers). There's quite a few experiments e.g. antenna matching where ballpark-level readings are fully adequate. For example, you can make a fairly decent GHz-ish antenna just by stripping the outer conductor from a coax cable for an inch, then cut down incrementally until the S11 minimum is at target frequency. Make two of them and I can show the inverse square law (-6 dB for doubling the distance in the far field), multipath fading (repeat same over a metal surface), polarisation (turn one antenna 90 degrees). This can be a real eye-opener for those who know RF only from equations, and a $60 VNA will easily pay back for itself in the next job interview.
  12. well... a 2.4 GHz VNA without RF frontend is not going to happen in 2020. Probably not in 2030, too. Even if we could afford ADCs and DACs at such rates to slap together, it would still make a pitiful VNA because real-world instrumentation is designed around the narrow-band nature of the signal path. It simply makes no sense to pay for components capable at sampling 2 GHz worth of spectrum, then discard 1.9999 GHz (assuming a 100 kHz IF filter). Oversampling can buy resolution but the exponents are not in your favor - in reality it's the difference between a GSM mobile phone you have to charge once a month and military SIGINT gear that ships with power supply on a separate trailer.
  13. One question you should answer for yourself (after deciding on Xilinx, which is more or less implied by the nature of the forum) is whether you want to go for plain FPGA or Zynq with embedded ARM processor. Reading between the lines of your post, I suspect strongly that your vision will map better to a conventional CPU-centric architecture with some FPGA accelerators than 100 % RTL (or even worse, a softcore CPU added as an afterthought after you've hit the wall and start to do some simple math on HOW MUCH EXACTLY will it cost to have every line of your code mapped to LUTs that wait most of the time for that particular line of code to get executed). Now my Zynq advice is a double-edged sword - the edge facing your way is more of a bludgeon (complexity) but it hurts nonetheless. Somewhat less so if you hire Zynq developers from the start but doing that without serious hands-on experience... opens up a can of worms or maybe a barrel.
  14. BTW, now that Altera pops up (BTW, please read the above "Bill's University" post carefully), there are boards that seem quite specifically made for your requirements list, since you're probably not the first one to use an FPGA for trading. You might search around what they use in network research. From my own past, I remember Terasic DE-4 (by now a very old board) and it does have 4x onboard ethernet, PCI, DRAM, even ships with jumper cables to cascade several boards via high-speed serial. But as said, selecting hardware should be the least of your worries (possibly pick one ethernet chip early if you intend to do spin your own high-performance drivers and TCP/IP stack). Digilent will probably have something similar if you search a little.
  15. Hi, I don't know if this applies to you but there is a very common pitfall, that is first doing isolated, abstract hardware / platform research and then only learning FPGA development. I am not certain with this statement - maybe it will work out for you. But I see a very high risk that it will not, even for bright people ... it's a bit like "buy a guitar, learn to play, form a band, become a rock star". For the vast majority, this plan does not succeed, and especially those who get stuck on the "buy a guitar" part.
  16. Hi, I have written a bitstream uploader for 7 series FPGAs which is included here (run the demo with an CMOD A7-35 board and it will upload its own test bitstream at startup). But it's not a turnkey solution in general. .NET exists in the mac world, AFAIK, so you should be able to build it. But it'll probably require some modifications to link dynamically with the mac's equivalent of the FTDI DLL. The Xilinx protocol at JTAG level is described in UG470. There are a few other projects on the web e.g. xc3sprog or urjtag that may be more general, once you figure out how to use them. xc3sprog will require minor changes for 7 series e.g. IDCODE.
  17. Very quick answer: If you want to learn FPGA, pick some entry level board and stop looking for shiny bits you could buy. That's the level ground before the learning curve even starts, don't waste any time there. If you're disciplined, a few LEDs and switches will keep you busy for months or even years. Just asking, have you considered Verilog? And BTW, "PIC" sounds like microcontroller, not FPGA.
  18. +1 on Raspberry ... it's absolutely not a toy but scalable. "Industrial" Linux does not look that much different. IMHO it's more important than ever, as e.g. PCs and smartphones are much less accessible than they used to be, now that security has high priority, OS-as-a-service changes every few months and Windows tries a support call every time my a.exe segfaults. BTW, a quick way to a "canned" 64-bit gcc on Windows is to install Octave. Then locate and run the "msys" shell that comes included. Command line "gcc" should work from there but I think it needs an explicit -m64 option, otherwise it would default to 32 bits.
  19. I'd grab any 64-bit command line C compiler e.g. TDM-GCC and start from a blank sheet. You need neither FPGA nor Xilinx nor any vendor-proprietary tools when it's about basics and learning. 64-bit "unsigned int" is your best friend. You can do the reference algorithm implementation using double format in the same file and have them always run side-by-side. For a small project, this methodology goes a long way. When it grows bigger, expect that managing the testcases becomes as much work as writing the code itself.
  20. But note, you need the correct electrical wiring. This is not supported by the majority of FPGA eval boards but I could always connect e.g. an FTDI mini module to a 3.3 V bank with jumper wires.
  21. Hi, most people working with FPGAs will have a reasonably capable PC under their desk. You can make that CPU power available for COVID-19 research when it sits idle through [email protected] The project has apparently been around for many years doing protein research. A summary is here. I found that on Windows, installation is pretty straightforward: Install BOINC create an account Start BOINC and select [email protected] It can be configured in many ways e.g. set it to use CPU power only if the machine has been idle for a minute. I leave it running at 100 % in the background and don't notice any obvious slowdown. From the few hours I've spent on the topic I got the impression that my old (but water-cooled and diligently overclocked) desktop still outclasses the other hardware I've tried: The newer laptop has good burst performance but goes into thermal throttling after a few seconds. ARM-based Android devices were far off, they probably have better power efficiency but lack the memory bandwidth (e.g. I see ~10 GB for 12 threads plus 2GB storage). So take this as a motivational speech that your FPGA design rig could be a valuable contributor. About one day of uptime got me on position 392.924 of the [email protected] worldwide ranking and I hope this post will motivate many of you to beat this šŸ™‚ Cheers Markus
  22. Hi, just having a quick look at the Arty schematic, there are for example a current sense monitors on the 3.3 V line (IC15, IC16), the regulator for the XADC (IC14), the 100 MHz oscillator and, most importantly, the flash memory (which usually exists in a 3.3 V and a 1.8 V variant). So I guess the answer is mostly "no", unless you fix a few things (among them probably the FTDI chip IO, which may be impossible). The 1.8 V supply topic is one I know only too well... The one Digilent board I'm aware of with variable IO voltage is FMC carrier S6. It's not exactly cheap with the FMC IO expander but I've used that one successfully. Also comes with an xc6lx45 component, where have I seen that name šŸ™‚ I'm sure there are others but most likely not the compact / cheap ones. My "go-to" board would be Trenz TE0725, still semi-breadboard-ish (hint, you can grab 1.8 V from one of the on-board regulators. Attach a wire to the large 1.8 V supply capacitor and route it to one bank's VIO pin). The modules with high density connectors usually require external VIO anyway so you are free to choose. Another candidate is Lattice ICE40-HX8K, they have 0 ohms resistors in the bank supplies.
  23. Hi, very quick thought: you don't necessarily need a spectrum "analyzer" for spectrum analysis. Your problem sounds like having to digitize the signal, make it available for offline processing. So the question I'd look at is, how can I get the signal from some measurement frontend (which you seem to have, something fiber-optic that outputs an electrical signal at the other end) into a PC. Then write software to process it. Hint: Eventually you may realize that the calibration for your test system is as difficult a design problem as designing the test system itself (maybe less so if you can base everything on frequency).
  24. one related comment: Accidentally unconstrained IO such as LEDs or switches can cause serious timing issues indirectly: They create difficult-but-not-impossible timing issues that then make P&R much more difficult / slow. Use e.g. false_path on any "don't-care" / asynchronous IOs. At the same time, double-check that you're bringing inputs in properly with an (*ASYNC_REG="TRUE"*) synchronizer, as this false_path would otherwise increase the risk of metastability events (after the first register) or just plain timing violations (if used directly). The worst case example is probably a dedicated "reset" switch that triggers synchronous reset everywhere in a large clock domain - with false_path there is a high chance that an event hits some parts at clock edge n, others at clock edge n+1. The synchronizer will avoid that.
  25. true - I should point that out clearly, the 480 MBit/s is the advertised number for the chip. Actual mileage may vary. Is it actually so that it would be achievable with a single port / device? I just noticed I was assuming the same 30 MHz MPSSE clock rate also for the 485 mode but I think the chip runs on 60 MHz internally so a single port might do at 8 bits / 60 MHz.