xc6lx45

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Everything posted by xc6lx45

  1. Hint, you can use a Zynq like an Artix, just disregard the ARM processor and integrate a UART on the FPGA fabric. As the board's built-in serial-to-USB connection is most likely hard-wired to the PS, you'll need an external serial-to-USB (e.g. "FTDI") board. Zynq is a difficult platform for a start from square one. the above-mentioned UART wiring being one of the first snags to run into. The regular FPGA e.g. on the CMOD A7 module is more friendly. Note that the simplicity of the Lattice board you mentioned comes from a heavy layer of code on both PC and FPGA side (bootloader). It's not necessarily a bad thing but be aware that it just postpones hitting the learning curve to the time when you need to leave the well-trodden paths. And then, things get messy (as compared to plain ol' "industry standard" JTAG connectivity).
  2. Some random thoughts: - I don't see why you'd use an FPGA in the first place. From a marketing point-of-view, an industrial-grade Zynq may be the perfect platform, but the learning effort is much higher than for a run-of-the-mill microcontroller. - if you have no or only superficial FPGA design experience, don't use an FPGA. If you can't decide, pick any rubber duck of your choice and explain it the concept of metastability in a few sentences. Is your explanation concise and rock-solid? If not, don't consider FPGA. If you have gaps in your understanding (e.g. the design is missing constraints), every synthesis round gives you a new roll of the dice for possible failures. - taking a shot in the dark: The most likely point of failure of any board you pick from this site is USB connectivity (probably does not matter). The next one is the voltage regulators. You can probably manage this risk (your design is unlikely to need much power in the first place, confirm by measurement and check that the FPGA runs cool). Still, looking at (expensive) industrial FPGA modules, the regulators take a lot of board space, for a reason. - if I had to pick a module from my own experience, I'd look at LPC1768 "MBED". It is very old still not exactly cheap, manufactured in large quantities and I'd guess they have ironed out the bugs by now (on-board Ethernet, just connect a socket with magnetics).
  3. xc6lx45

    Advanced topics

    one recommendation, but check out whether it works for you: Keshab K. Parhi "VLSI Digital Signal Processing Systems: Design and Implementation" It's a very old (pre-FPGA) book, but it'll be as relevant in 20 years since the theory does not change. You can find a condensed version in the lecture slides. Pick what appears interesting: https://www.win.tue.nl/~wsinmak/Education/2IN35/Parhi/ ------- Reading through the Xilinx documentation might be a good idea. There are those people who read manuals and those who don't. Usually it's easy to tell the difference... I'd skim quickly over parts that don't seem relevant at the moment (which may be 99 %, definitely too much material to read cover-to-cover) and spend time with those parts that seem interesting or immediately relevant. ------------ For a practical example regarding timing, speed optimization, critical path, you can try this simple project: implement a pseudorandom sequence (e.g. 9 or 24 bits) and compare against a same-size number that is an input to the block (not hardcoded, e.g. set by switches). This is a simple AD-converter and you can test with a LED that it works. Then try to run at as high clock speed as you can manage e.g. 300 or 400 MHz. Understand all the warnings, fix those that are relevant (some are not but you should understand why), especially the ones related to inputs ("switches") and outputs ("LED").
  4. xc6lx45

    I bricked my CMOD-A7

    You might try to take an old USB cable and put an amperemeter into the 5V wire. I suspect you'll observe that current consumption starts around 80 mA (the FTDI chip waking up) then dropping much lower when the FTDI chip shuts down. I've seen this pattern on other designs when there are issues with USB / power supply. Most likely it has nothing to do with Flash. Hypothetically, I could flash a design that draws more current than USB can provide, and would cause the FTDI chip to run out of juice and shut down. Maybe the PROG_DONE LED goes on for such a short time that the eye does not notice. In this case, the paper clip trick should be sufficient to bypass Flash boot once. And as mentioned above, you can access the boot mode pins, e.g. solder a wire to the FPGA end of the resistor.
  5. xc6lx45

    Offline Installer

    I might chime in with an opinion here: This problem will generally become more severe in the future now that Windows 7 is EOL and obviously unsafe: There is a big number of (pre)-Windows 7 based embedded machines etc out there that came with a 6- or 7 digit price tag and must be isolated from the web nowadays. I am personally aware of one large vendor who is totally oblivious to this problem (e.g. trying to stream a welcome video with their driver installation and failing, relying on 256-bit encryption which is not included in Vanilla Windows 7 as found on a recovery partition) and it has cost them dearly. In a trade fair or marketing presentation, everything is new and shiny but dinosaurs walk the factory floors... which is BTW the reason why GPIB needs so heavy cables 🙂
  6. xc6lx45

    I bricked my CMOD-A7

    Thinking aloud: Is it even possible to "brick" an Artix from Flash? On Zynq it is if the FSBL breaks JTAG, and the solution to the problem without boot mode jumpers is to short one of the flash pins to GND via a paper-clip at power-up. But on Artix? Can't remember having seen such a thing. Through EFUSE, yes, but that's a different story. If you like, you can try this if it's a 35T (use ADC capture at 700 k, it stresses the JTAG port to capacity). For example, it might give an FTDI error. Or if it works, you know that JTAG is OK.
  7. So you have working fixed point RTL (sounds like quite an achievement BTW) and want to hook it up to the Microblaze. I'd look for info how to implement an AXI lite slave. Vivado has several built-in options to help with that - not necessarily the best way, depending who you ask, but it did work for me. For example "Tools / Create and package new IP / create a new AXI4 peripheral". Finish the wizard, then take the Verilog file with its implemented dummy registers and continue editing it by hand. My first step would be - plain registers for input data - a write-sensitive registers for the final input data word or a dedicated "control / start" word that resets/starts the processing state machine and clears an "output-is-valid" bit - a register for the first result that blocks on read for "output-is-valid" from the state machine - plain read-only registers for the remaining output data The control flow of the program is simply "write data, read results, repeat". I'd sell this as "minimum-size approach"... It can be improved in many ways (e.g. output-side FIFO, input-side FIFO, pipelined processing in RTL, full AXI / stream, ...) depending on your specific requirements e.g. throughput, bus utilization, avoid blocking the CPU.
  8. xc6lx45

    Verilog Simulator

    >> student/beginners try to use these non-synthesizable constructs to generate "programs" rather than "designs". Students, beginners and most of industry for testbenches, making pitiful noises from the pain but using it nonetheless. Yes, Verilog is horrible and could be improved in oh-so-many ways, like most successful languages engineers use to get their work done before the deadline (perl, Matlab, C, Excel / Visual Basic, ...). I think you are driving a methodology that is very different from typical industrial use (where designers must deal with a large number of simple problems instead of working on a single hard one for weeks and months). Maybe you should add a disclaimer, like "warning: following this to the letter may make you look really stupid in a non-academic job interview".
  9. xc6lx45

    Verilog Simulator

    As a 2nd opinion, I would not recommend Verilator to learn the language. It does work on Windows (MSYS) but I'd ask for a good reason why you need Verilator in the first place instead of a conventional simulator. Have a look at iverilog / gtkwave: http://iverilog.icarus.com/ It works fine from standard Windows (no need to create a virtual machine). You'd call it through the command line though (hint: create a .bat file with the simulation commands to keep them together with the project. Hint, the abovementioned MSYS environment is pretty good for this, e.g. use a makefile or shell script).
  10. xc3sprog works for flashing with minor modifications e.g. IDCODE. I have used it on Artix. Setting up the compile environment is quite a bit of work, though. If that helps: for uploading to volatile memory (until the next power cycle), I've got source code here.
  11. xc6lx45

    Large Spectrum Generation

    (OT) A curiosity, I've tried to use it for PWM once but the DC average observed on the brightness of a LED seemed to depend on the bit position. Has anybody made similar observations?
  12. xc6lx45

    Large Spectrum Generation

    Hi, there are two important corner cases with regard to the power you're outputting: - slow sweep (wobble / FM): the signal is continuous-wave, its peak-to-average is as low as physically possible. This will output the highest power within a given amplitude limit and (oversimplified) optimally use the dynamic range of the signal chain. - single pulse: use a sample stream ... 0 0 0 1 0 0 0... (which has constant spectrum) or use the impulse response of a suitable bandpass filter. This results in the shortest possible signal within the limitations of the time-bandwidth product (see e.g. "band-limited pulse" on Wikipedia) but the signal has a high (bad) peak-to-average ratio, thus (oversimplified) requiring higher dynamic range in the signal chain. Examples for the two methods are a conventional RF vector network analyzer (continuous wave, at least traditionally) and pulse-based time domain reflectometry, e.g. Teledyne LeCroy Sparq instruments. What can work well is to use a bandpass-filtered (pseudo)random sample stream, possibly with additional clipping / filtering rounds to improve PAR. But at the end of the day, it depends on what statistics of the signal matter how much in your application, e.g. autocorrelation, amplitude PDF, actual spectrum shape. Matlab (Octave) would be my tool of choice for algorithm design, not RTL
  13. OK, never mind the soundcard idea 🙂 as said, I had not studied your requirements in depth. Just wondering, you want to use the AD2 as a module, not as test instrumentation? With the budget you mentioned, subcontracting a customer-specific FPGA image is not unheard of (this comment for FPGA-based hardware in general, not Digilent-specific) If your requirements are somewhat flexible: The Xilinx 7 series devices (Artix, Zynq, Spartan 7) have two built-in, independent AD converters with 1 MSPS, 12+4 bit . The ubiquitous FTDI USB chip can manage close to 30 megabit per second. If you can re-spec to those limitations, modules start at $50, give or take some (e.g. CMOD A7). I implemented a fun project that demonstrates dual-channel 700 ksps streaming data acquisition via USB on the CMOD A7 module (can use that e.g. to quickly check whether streaming is still reliable when other software is running on the PC). Probably performance is too low, but the hardware option would be very cheap. If that matters, roundtrip latency slightly below 125 microseconds is possible this way (this is my USB interface code but it's not for the faint-of-heart, 5x faster but by necessity much more complex than plain UART-based IO) I'm personally wary of building on top of USB with its DNA deeply rooted in consumer electronics (GPIB anybody?). That said, if I had to come up with USB streaming data higher than 30 MBit/s (standard FTDI chip in serial mode) but still cheaper than your expensive 2 GBit/s bus that is quickly demonstrated as a prototype, I'd grab one of those modules and use it in parallel mode. When that works reliably, making a custom PCB with converters, some FPGA module as glue logic and the FTDI module seems like a routine design job, with the expected difficulties mostly on the software side (PC side code, RTL and the protocol in-between). My $0.02...
  14. Hi, I hope someone will be able to solve your problem. That said, ... >> So my capture time was almost 5 times too long. I confirmed that even with two pulses the system cannot transfer fast enough >> python >> improve performance? Is there something wrong in my code? Am I misunderstanding the capabilities of the AD2? If the system had a USB 3.0, ... I suspect your job calls for hardware in a different price segment. Take this just as a general opinion without having studied the details of your specific problem. An NI 5840 (or 5820 if you don't need its RF frontend) would turn it into a routine job, more or less. Obviously, priced very differently, just pointing it out as an instrument that I know works well. Some PCI AD/DA card would probably cover the functionality you need but think twice about synchronizing multiple devices with accuracy sufficient for TOA measurements, and long time stability - here be dragons... If I needed something cheaply, I'd look at 192k sound cards, they can do reliable streaming data at low price. But the bandwidth will limit your Doppler range severely, plus a null at DC (offset Tx/Rx LO might fix that but yes it starts to look like a bad hack).
  15. Cool! 7 Series should have sufficient horsepower for a decent convolution reverb / cabinet model, for example.
  16. xc6lx45

    LVDS in CMOD S7

    disclaimer, I haven't tried a similar thing and did not dig into the documentation. But I think you need a HP bank (not HR) and question is, does a low-end board support it. Check the warnings. See https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf page 91: The LVDS I/O standard is only available in the HP I/O banks. There used to be LVDS 3.3 but not on 7 Series anymore, AFAIK (differential modes, yes, but not "LVDS" specifically).
  17. PS not saying that the idea of 400 MHz SPI is necessarily meaningful 🙂 just talking about the internals to the FPGA pin, not what's realistic on a PCB with 1/10 inch headers etc.
  18. Hi, quick answer: For someone with FPGA design experience it is not a big job (the PC side interface for configuring parameters etc is probably more work than the SPI core itself). BUT, don't underestimate the difficulty of getting there ("Python?", I read between the lines that you need it as just a tool, not a task that may require a man month. Check early what is realistic - whether or not the hardware can do the job is not necessarily the right question. A FPGA can do "anything", more or less using HDL) It has built-in PLLs so you can generate any frequency you like. 100 MHz is fairly straightforward, 200 MHz will need some extra effort, 400 MHz should be feasible in the hands of someone who knows the hardware (SERDES) . As many slaves as you have IO pins for (check the voltage, though). SPI is fairly simple, it sounds like a fairly compact project (UART for PC IO, state machines for control around a bunch of shift registers). But again, reading between the lines, be careful what is achievable with the amount of time you are willing to invest.
  19. just an observation: Most people would probably implement this around a shift register, instead of muxing a single bit. Functionally it would be the same (of course, assuming timing is met).
  20. >> Don't know why my tower doesn't work but my laptop does might be a bad USB card or interface. For example, the polyfuses in the voltage supply line are notorious for their even infinite memory effects. Also, the specified number of cycles for USB connectors is ridiculously low. USB from the PC shop is consumer technology - a USB card can be had for $5, an industrial GPIB card is $500 even though the former is even technologically more advanced 🙂
  21. Hi, purely as an idea: If you have the 35A-variant, you could try to run this (link below, use the latest link from the last posts). You may need to install FTDI's standard driver, if not present. It uploads a bitstream and exercises USB with regular traffic e.g. set ADC rate close to 1 MSPS and it'll use about 25 MBit/s. The application will immediately close with an error if USB fails. There may be a virus warning e.g. with bitdefender which is to the best of my knowledge false.
  22. xc6lx45

    XC7A15T-1CPG236

    Hi, can you find a CMOD A7 version with the bigger FPGA (35T)? They should be mechanically identical.
  23. one hint: You can zoom in (I think it's the middle mouse wheel) and at some level the primitives become visible. You'll see that for a small design the utilization is very sparse so the picture does not give a good visual indication of used resources (use the design report). Using inference (via the "*" operator) is generally a good idea. Read the tool output / warnings, it'll tell you a lot about what happens internally. The DSP48 is happiest if there are a few registers in the path so it can absorb them into the DSP48's internal hardware registers. This matters if you intend to go beyond maybe 100 MHz, give or take some. The same applies to BRAM, "inference" works pretty well and it's time well spent to figure out how it works.
  24. Have you considered installing Linux? E.g. a virtual machine or a Raspberry PI. $0.02: Learning interview questions is an immensely popular topic on the web but I'm sometimes wondering how much point there really is. So the skillset you are presenting has been obtained from a book over a few days. Surprisingly, the company is still more than happy to hire you. Question is ... do YOU want to work for this company? Lots of people hate their job. Every day. And this starts here ... think.
  25. what I'd do is use the template for an AXI-Lite slave (appears in the graphical view as RTL block and is recognized in the address editor), route one of the template registers to a LED. Then use this to "pipe-clean" the tools, for example go through the whole PS7 setup once without templates (keep DRAM as it's fairly complex but the other settings I'd rather understand when working with the chip). Can't say whether the "various" ways are that more interesting but for example you need a MIO-driven LED to emit blink codes from the FSBL because the PL isn't yet awake (hopefully you don't need this anyway. Take it as advance warning that running a design from flash is not necessarily as straightforward as e.g. on Artix...)