xc6lx45

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Everything posted by xc6lx45

  1. xc6lx45

    coorruner II operation

    Hi, disclaimer (I take it you are not an FPGA engineer): Some of the terminology in your post is fuzzy (there are no "programs", strictly speaking, but I believe I understand what you meant). Please have a look at this https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf page 14 "quality and reliability parameters", ] NPE Program/erase cycles (Endurance) 1,000 So the manufacturer guarantees this device can be reprogrammed 1000 times. More, and it may eventually break.
  2. xc6lx45

    Cmod A7 SRAM project INSIDE

    You could move the body of wr0 and rd0 into idle state. As an optimization, this would reduce the write cycle time from 5 to 4 (+20 % throughput). But, more importantly: Right now, "busy_signal_output" comes up only two cycles after start_operation. If the surrounding circuitry isn't aware of this, it might check in the next cycle, see no "busy" and assume the operation is complete. edit: and mixing bitwidths 3, 4 and 5 (4:0=5) in the "localparam" statement seems dangerous.
  3. xc6lx45

    Cmod A7 SRAM project INSIDE

    Hi, I just had a very quick look. This is maybe more about style and opinions, but is there a reason to use a blocking assignment for the state variable? To me as a human reader, this code if(~start_operation) state_reg = idle; suggests that the new value of state_reg would still be important for code further down during the same clock cycle. Functionally, it should be the same, though.
  4. xc6lx45

    Diving in

    ... a slightly longer answer, if anybody is interested (analog mixing with square wave LO): One way is to look at the Fourier series of the square wave as a sum of sines at frequencies f, 3f, 5f, 7f, ... and to a lesser extent 2f, 4f, 6f from implementation imperfections. Then think of the mixer as linear multiplier, and use superposition (the distributive property of multiplication) for a*(b3+b5+b7+...) = a*b3+a*b5+a*b7+... Hint, if anybody wants to formally go through the math, it gets much less messy with cos(x) = (exp(ix)+exp(-ix))/2 aka DeMoivre. So you really get multiple frequency translations instead of one. What remains to be done is to manage the input signal energy at those frequencies I don't want, with a filter or narrow-band antenna. In the digital world, you'd always use a sine wave.
  5. xc6lx45

    Diving in

    >> it seems like it's very desirable to have a pure sin wave, Welcome to the world of radio engineering :) Very quick answer: Many modern receivers (e.g. take your cellphone) use a digital divider for LO generation that outputs a square LO signal. It actually gives higher mixer gain (which is good for noise) since the "switches" in the mixer conduct 100 % of the time and improves balance issues. The downside is, you get strong spurious responses at n times the LO frequency, which should be suppressed by filtering at the antenna side, before the mixer. But this is one problem from a very long list that you can probably ignore for a while. Generating a square LO is straightforward - simply use the clocking wizard to instantiate an MMCM/PLL. The chip does include LC oscillators (of which Colpitts is a textbook example) and they are digitally programmable. They can also provide 90 degree phase shifted outputs from a built-in divider. BTW, if you downconvert the ADC signal in software: You need a _decimating_ lowpass filter. Either that, or the number of MAC operations skyrockets (calculating samples that are mostly discarded).
  6. xc6lx45

    Diving in

    Looks like you found the UART discussion in the other thread, I think I see where this is heading Using the FPGA for an downconverter frontend from a direct sampling ADC is relatively straightforward: quadrature NCO, multiply the signal with sine / cosine, lowpass filter both products and send to PC as I and Q. Note, there are fairly decent ADCs on the modern FPGAs (Artix, Spartan 7) that are capable of sampling I and Q channels in synchronized mode. Mixers are cheap - If I had to hack up something quickly, I might think about using the FPGA to generate downconverter LO signals (possibly in quadrature) for external Minicircuits ring diode mixers. Just thinking aloud... (this is creative ham radio hacking, not something I'd expect to see in a self-respecting product implementation)
  7. xc6lx45

    Diving in

    Hi, a little bit of warning: "Genuine" SDR on FPGA is a difficulty level far beyond "enthusiast" range. When FPGA implementation comes in, you should have a clear understanding of the algorithm side. It's the wrong technology to learn SDR. Until then, use Matlab / Octave / Scilab / Python / whatever to prototype ideas. Even if I run out of CPU horsepower and start writing optimized C code / throw in SSE intrinsics / convert to GPU-code / use grid computing / ..., it is still much more straightforward to work with than FPGA. One simple reason is that I can just write everything out in 32 bit floats, no need to touch fixed point math. Or take the slow compile cycle and lack of accessibility for internal signals. Those are actually the very same reasons why I've grown so fond of Octave over the years.
  8. xc6lx45

    Cmod A7 oscillator question

    Hi, could you maybe "open the implemented design" and check the timing reports? With your screenshot, this is a blind guess: One fairly popular mistake is to define a clock twice, once in the constraints file, once via the MMCM IP block. In this case, you get "inter-clock" failures ("from one clock to the other") between two clocks with different names that are in reality the same. A solution may be to disable the clock definition from the constraints file, keep the one from the clock wizard. If you want to debug it yourself: Look at the clocks in the timing report and try to explain what every one of them means. If there are some that don't make any sense, this may be the culprit.
  9. xc6lx45

    ARTY FPGA

    Hi, search for "XADC". Examples shouldn't be hard to find, it's a popular topic.
  10. xc6lx45

    Cmod A7 SRAM project INSIDE

    Hi, generally I appreciate enthusiasm. But the amount of text you have written, including transistor-level SRAM cell schematics, seems grossly disproportionate to the actual length of Verilog code Seriously, you have not implemented a "controller". Not in any conventional meaning of the word. Now that's not very diplomatic of me. Still, I'm writing this in the spirit of constructive feedback. Harsh words, but then one of the worst things is people telling "you're doing great" when you are not. How should I start... Think of writing a "controller" as composing a symphony. It may be a long one or a short one, loud or quiet, a good one or a bad one but it's definitely not something I'd try in my first week at music school. Why, because it better be perfect. It's supposed to turn a complex device into a simple one, anticipate all the problems and make sure they don't happen. Example for "problems": your module implements combinational routing of address, outbound data and write-enable signal directly to the chip. The chip requires (datasheet, drawing page 14 and table page 12) that address and data are valid at least up to the deassertion of enable, or longer (very strictly, this is stated as t_ha/t_hd = 0 ns). For your "controller", the output timing is totally at the mercy of the driving signals. And it even gets worse: For the FPGA design tool "synchronous logic" world, only the level at an associated clock edge matters. What the signal does in-between is don't-care. Not being aware of this is a fundamental misconception of modern "synchronous logic", and suddenly straightforward and systematic engineering becomes black arts. Here is the long story. In your design, it means for example the write-enable signal may go "blip!" between clock cycles, courtesy of the outside circuitry. And this is totally OK for the design tools. But not so for the SRAM, which will randomly write garbage.
  11. xc6lx45

    Nexys Video HDMI in problems

    Hi, this isn't specific to any particular card, but in the past there have been problems with HDMI reverse biasing. That is, a situation where it is unclear which device is allowed to supply voltage at what time.
  12. xc6lx45

    Noise on JB (Arty A7)

    Hi, have a look at the schematic, page 1: https://reference.digilentinc.com/_media/arty:arty_sch.pdf apparently, JA and JD do use 200 ohms resistors, but JB and JC don't. I suspect you're observing not "additive" noise (like, from a switching converter) but signal integrity issues, caused by the signal itself (say, reflections on a long, unterminated wire). There are several reasons why a series resistor will make it look better.
  13. xc6lx45

    Noise on JB (Arty A7)

    Hi, AFAIK, PMOD ports have a 200 ohms series resistor. Did you maybe switch to an unprotected FPGA output (no added resistor) when the noise went away? This wasn't clear from reading your post.
  14. xc6lx45

    Nexys 4 Ring Oscillator

    This is actually cool stuff. Please take this as constructive input on academic research: A very straightforward problem is that P&R isn't fully under user control (even if I constrain the sites). There's a risk that performance tested on an empty device is optimal (shortest routes, highest frequency) but degrades as design density goes up and path lengths increase. My main concern with "innovative" approaches is that we can never prove that it works reliably, in all device process corners and across the life span of the device. The basic, advertised features (e.g. the LC oscillator in an MMCM) are validated extensively, both in theory (e.g. sufficient margin for the loop stability factor, to pick one parameter out of a very long list) and hardware validation (say, "high temperature operating life" HTOL testing. Ovens full of tightly packed devices that are then tortured for weeks or even months). For the chaotic oscillator, we have to rely on a "cowboy proof" - it worked yesterday, it works today, it'll probably still work tomorrow Here's a random link about CMOS reliability, relatively recent (2016). The question I'd ask is, are we subjecting the device to stress that will cause it to change over time. Or more precisely (any semiconductor changes with time => Avogadro's law, e.g. diffusions wander), that will detectably change the analog behavior. For digital operation, your chip is designed to be maximally robust. But this is not a digital circuit, so there may be nasty surprises when for example previously independent random processes suddenly get correlated, say via supply line coupling. Deterministic post-processing cannot add entropy, suddenly my RNG leaves finger prints... Example for stress, Fig. 1.2, change in threshold voltage (which will obviously have some impact on this pseudo-analog circuit). I'd also keep an eye on current consumption (electromigration) when chip-internal signals are becoming ill-defined in continuous operation on a large scale. Bad cryptography kills people - maybe I wouldn't consider it for (Xilinx paper) "... probably the most demanding cryptographic applications"... But, it's a cool little circuit, shows what FPGAs can do besides "mainstream synchronous logic" .
  15. xc6lx45

    Cmod S7 Spartan 7 Board Power Consumption

    I think this really depends on what you are doing with it. Is the USB chip woken up? Are you using PLLs? Are you utilizing a dozen gates or the whole chip for bitcoin mining? If I had to guess a number, I'd go for 100 mA from USB 5 V in unprogrammed state.
  16. I think the term propagation delay is typically used for a single logic block. Clock latency as in your drawing shows specifically the end-to-end length of the clock tree. For Xilinx, https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf does not contain the word "latency". The reality might be actually more complex: See "Clock Network Deskew" on page 72: Nowadays, clock rates are so high that we may not be able to simply define the reference phase at the input of the clock distribution network, and have the clock "latency" eat away the timing budget: In many cases, designers do not want to incur the delay on a clock network in their I/O timing budget therefore they use a MMCM/PLL to compensate for the clock network delay. So we use a dummy delay to advance the PLL phase by the nominal "latency", therefore moving the reference point to the end of the clock distribution network.
  17. xc6lx45

    Old Knowledge seeking advice

    Think of it as a wire wrap board the size of a basketball court that can reach 100..200 MHz. Price includes an army of well-trained virtual wire wrapping monkeys, so well trained that many folks have no clue what they are doing. This is where the learning curve gets steeper🙂
  18. xc6lx45

    Old Knowledge seeking advice

    Hi, if you have the endurance to get into FPGA technology (no disrespect but the learning curve seems to throw most people off before they ever use one for something useful), the cheapest board can keep you busy for months, possibly more. You may actually realize at some point that the hardware isn't even that important except for motivation - it just tells you "sorry, this doesn't work" and then it comes down to simulation to figure out why... Some 7-segment displays, switches etc are nice, but in the end one single LED is enough (this worked at least for me, plus later UART to connect to PC, very few boards don't provide the required hardware). You can download Vivado Web edition completely for free, and start all the fun, minus the hardware. Cost: $0.00 A Raspberry pi might be another thing to consider. Belongs into every household, as far as I am concerned 🙂 this thing is amazing.
  19. xc6lx45

    What is the memory part for the Cmod A7-35T ?

    I can't tell where the letter "0" is coming from. I checked under the microscope, it is also on the component. Most likely, the row you selected is the best choice. If programming and verify succeeds, I'd just go with it. This may not be the preferred approach if your application targets pacemakers, self-driving cars or thermonuclear missiles...
  20. xc6lx45

    External antenna CHIPKIT WIFIRE

    Hi, for a lab prototype I wouldn't think twice, cut the upwards-facing trace with a scalpel and attach a thin semirigid coax wire. Most likely it is not 50 ohms so performance will be impaired somewhat, but then I bet the VSWR seen by the module in a real-world application is also this side of infinity... Let's hope someone from Digilent comments, but the module seems to be approaching EOL anyway ("not recommended for new designs"), not sure how much I would realistically expect
  21. xc6lx45

    Accuracy specifications of Impendance Analyzer

    Hint: The Matlab / Octave function "fminunc" or "fminsearch" can work miracles in finding parameters of an equivalent network. In the past, I've used Maxima CAS to get the Laplace-domain input/output equation from nodal equations, then "stringout" to import the result into Matlab and "fminunc" to fit the parameters to measured data. This doesn't even need phase, just magnitude data (as long as it's minimum-phase type)
  22. xc6lx45

    Noob question on Basys3 Board

    Hi, see page 68 here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug908-vivado-programming-debugging.pdf "BITSTREAM.CONFIG.UNUSEDPIN Pulldown" Means, unused pins are driven by a weak pulldown. Most likely, this explains your observation.
  23. xc6lx45

    100 MHz clock synchronization between two AD2

    I can only tell you this much that sync'ing multiple instruments is by no means a trivial problem, at least as long as external triggering is concerned. Which means, in other words, starting both boxes at predictably the same time. The problem is a race condition between the (asynchronous) trigger signal and each unit's interpretation of the reference clock. There is always a possible trigger time instant, where a very small delta moves it over the edge on one side but not the other. So you have a timing ambiguity of 1 sample in the mathematically ideal case. With real-world instruments it is often more because of implementation limitations (generally, not speaking about AD2) and I either let one of the instruments generate the trigger (which is then synchronous) or import it into the reference-synchronous "trigger" clock domain of the instrument (which is often 10 MHz aka "trigger resolution of 100 ns") and re-export it from there.
  24. That's the spirit And I'm sure people will be willing to help when you're stuck. Just as a reality check: writing that above mail took me about 30 min (for whatever reasons, maybe it just beats crossword puzzles). How long did you spend to read it?
  25. >> Can you please do the modifications that you mean on my initial C code posted here and reply to me that might help to overcome this problem?? I'm sure I could but it might be disrespectful to lots of other folks on this forum eager to do your work for you. I suggest let's wait and give them a chance