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Everything posted by xc6lx45

  1. True - the added noise breaks up "coherent" quantization error and spreads it evenly across the bandwidth (where I can usually filter away most of it digitally) Most analog designers will scratch their heads if given a minimum noise specification for the driver amp but hey, it's physics πŸ™‚
  2. but watch out, the resolution may be closer to 8 bit than the 16 bits mentioned in the original post. This is at least what I got with a GSM signal around 900 MHz (plus a frequency offset I had to correct by resampling, since the average scope does not have a reference clock input). Your mileage may vary. I had more luck the other way using an RF vector analyzer with IQ inputs as a very expensive oscilloscope but that's about 180 degrees out of phase with the topic πŸ™‚
  3. >> But it will cost me a bomb and I need to be sure I am investing on the correct thing. My entry for the "shortest answer" competition: Get a CMOD A7 or similar. It's dirt cheap - consider it disposable and save the idea of buying something "more capable" for long term motivation. Starting with an expensive board, then being afraid to use it for fear of breaking it does not help with learning. Zynq is significantly more complex than Artix and the FPGA part is less accessible.
  4. Before you spend money, sit down for an evening and read through forum posts. In a nutshell (see the earlier post for an example, the wideband-/narrowband configuration thing): Eval boards are not modules Sometimes it works but there is a high risk involved (such as, you place your order based on studying board revision X and get revision Y, which is completely different). If the FPGA is needed only as adapter, have a look at digitizer cards in PCI or PXI form factor.
  5. You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.
  6. Just wondering, are you aware of Xilinx Webpack? It needs a license but you can just request it.
  7. Hi, since you asked for (FPGA) RAM, check out the "inferred memory" concept e.g. here: https://forums.xilinx.com/t5/Synthesis/UG901-distributed-vs-block-ram-inference/td-p/775730 if you open Vivado main window, then "Tools" menu, there is an option "Language templates". You may also find some useful material there (and some other that is very specialized). One advantage is that these examples are specific for FPGA, whereas generic VHDL instructions may be targeting ASICs or simulation, which are less restricted than FPGA.
  8. xc6lx45

    Power consumption

    what do you think? What does actually cause the power consumption in modern CMOS?
  9. Hi, >> I understand the if the pin is an output, then current should exit from it Most likely, your understanding of the output cell is wrong.The point is the "C" in CMOS, "complementary". Look at the first picture in the link - there are two (MOS) transistors, one to positive supply voltage and one to negative / GND. The pin can source and sink current. This is the magic behind almost all modern digital circuitry. And if anybody wonders what would happen if both switches would open at the same time. Magic smoke appears πŸ™‚
  10. Maybe you want to re-think Arduino, with a professional technical background. It may be that a Raspberry Pi with the "wiring" library is more useful long term. Just as a note, the guitar FX is a surprisingly challenging project, if it's supposed to be borderline useful. E.g. "aliasing" - you bend a note up and half of the little monkeys in your sound bend down at the same time. It gets tiring
  11. Then your bandwidth is 6 MHz, not 60 MHz (according to what's printed on the probe). Try to set it to x10 mode. The divider allows for a wider bandwidth.
  12. are you maybe using a low-speed analog output with 200 ohms series resistor? Check the schematic of the board for a direct output.
  13. xc6lx45

    Cmod S6 - Multilayer?

    You might go to Texas Instruments' site (or AD or both) and find documentation for some $500 high frequency ADC or DAC eval board as example to study.. There's nothing wrong with copper planes, generally. Free-standing structures (such as non-connected filler polygons) can be bad, if they resonate. So are loops if the driving wire spans an area together with the GND return wire (for which the ground plane is an obvious solution). The worst resonators have high quality factor meaning loose coupling meaning it can be surprising how the energy managed to couple in. There's no such thing as too many ground vias... Note, your ground plane can do very interesting things in combination with the metal box it's in (resonant cavity) but that's a different story.
  14. laughing out loud ... Formula-1-performance is niche business, combine harvesters bring home the money, walking barefoot is the norm. And why not, I'm even discouraging people to touch it as long as a UART does the job. Same as with fast cars, speed is largely overrated. Those who know otherwise, you know who you are πŸ™‚
  15. >> Is there a strategy that targets the re-use of logic? this is a slightly different question, but can help the tools with timing: Sometimes I need to replicate logic that starts with an input register on the same data for all instances (e.g. multiple blocks using identical high-frequency counters as internal timebase). The tools will recognize them as logically equivalent and try to use one shared register. This is bad, when the downstream logic is timing-critical. In this case, I can manually flag the register as "DONT'T TOUCH" so the replicas are preserved and placed closer to the critical logic. Optimization would eventually reach the same conclusion after thinking long and hard. There is a "-keep-equivalent-registers" option that makes this the default. The "rebalancing" option is under Synthesis options "-retiming".
  16. is this the absolute group delay or the delay uncertainty? The latter you can calibrate out. And I can interpolate mathematically between samples in a way that is indistinguishable from a faster converter, for a bandlimited signal. Absolute latency, yes, the sample rate sets an obvious limit, but read the converter datasheet carefully (internal processing latency). Now I'm guessing on what you're trying to achieve: note that sampling rate has nothing to do at all with time-of-arrival estimation error (theoretical limit: the so-called "CramΓ©r-Rao" bound. It depends solely on the spectral shape and some signal-to-noise ratio).
  17. Hi, it may help to close timing. But most likely it's a dead end, for several reasons: P&R is at the end of the design process. It fails here but the root cause lies somewhere else most likely (blind guess, assuming from the nature of the question that you're not a power user), the problem lies in the constraints. Specifically, a missing "false_path" to timing-uncritical IOs like switches or LEDs. This can be a timing killer, because it leads to an impossible job for the tool. inserting pipeline registers will most likely fix it. In most cases (no closed loops, no rigid latency constraints) it's fairly easy to insert single-cycle delays across a "cut plane" through the design, leaving the functionality unchanged. Regardless of the strategy, check that "register rebalancing" option is enabled even if you manage to close timing once by tool options, the design will be difficult to work with, long P&R times and no guarantee of success. When squeezing a commercial, large volume design into the smallest possible device this may be worth the trouble, but not during R&D unless the design is "pushing the envelope".
  18. Hi, I suspect you're using slow default options for bitstream generation. Increase the clock rate and enable bitstream compression. It should be much faster.
  19. BTW, if you use a 1 MSPS ADC for 10 kHz bandwidth, you may gain the two bits from oversampling gain. E.g. accumulate 64 samples and use sum[21:6]. It causes some deviation in the frequency response "sin(x)/x", if in doubt use less averaging than theoretically possible. Just be aware that the smooth early learning curve is designed carefully into some technologies e.g. Labview. FPGA in general is not one of them... No free lunch here. I'm still hoping someone will say it's possible with AD2.
  20. as a general comment, it's fairly common to have unplaced components on a PCB, especially a sparse one where there is no pressure to reduce size. Your readings are all over the place - I doubt that with 12 V (0.12 V?) on the 5V net and 3.3 being the new 1.8 (C181) there would be any magic smoke left inside the board... But with a proper multimeter (make sure you have a good connection to GND on the black lead), I see a good chance that you'll be able to spot the problem, basically if any net is significantly off its designated value.
  21. An MBED LPC1768 might work. You need to connect Ethernet magnetics, but that's more a mechanical issue (flying wires worked for me). The C code below reads a file "config.txt" from the MBED's USB drive, which is a simple way to set the IP address by editing the file in notepad.exe. char buffer[256]; char ipAddress[256]; char subnetMask[256]; sprintf(ipAddress, "%s", ""); sprintf(subnetMask, "%s", ""); int port = 7; FILE* f = fopen("/local/config.txt", "r"); if (f != NULL){ int n = fscanf(f, "%s", ipAddress); if (n <= 0) goto endOfFile; n = fscanf(f, "%s", subnetMask); if (n <= 0) goto endOfFile; n = fscanf(f, "%s", buffer); if (n <= 0) goto endOfFile; port = atoi(buffer); endOfFile: fclose(f); } EthernetInterface eth; eth.init(ipAddress, subnetMask, ""); eth.connect(); printf("IP address: %s (configured: %s) port %i\r\n", eth.getIPAddress(), ipAddress, port); TCPSocketServer server; server.bind(port); server.listen(); while (true) { printf("\nWait for new connection...\n"); TCPSocketConnection client; server.accept(client); client.set_blocking(true, 0); printf("Connection from: %s\n", client.get_address()); client.send_all(">\r\n", 3); // === main loop === while (true) { // === read data from socket === int n = client.receive(buffer, sizeof(buffer)); // === detect connection break === if (n < 0) goto conn_exit; // maximum length of a single reply. Anything longer will be split. #define MAX_PACKETLEN (1024) // maximum length of a single message to guarantee there is enough output buffer #define MAX_MSGLEN (16) char bufOut[MAX_PACKETLEN]; // === iterate over input characters === int ix; for (ix = 0; ix < n; ++ix){ ... work on buffer contents ... send reply: client.send_all(bufOut, nInBuf); } // for input character } // while connection conn_exit: client.close(); } it needs this ethernet library (there may be several) /* EthernetInterface.h */ /* Copyright (C) 2012 mbed.org, MIT License
  22. >> problem with the clock BTW, UARTs are pretty robust towards frequency error because the sampling instant re-syncs every byte. Electrical interference could be an issue, since there is more noise on the power supplies when the CPU is busy. What I'd try is look at the signal with a scope, or add some resistor to ground. A ferrite choke might also help, if it's a noise problem.
  23. A couple of thoughts: What you're looking for is "streaming" data acquisition. It's fairly routine with industrial test equipment e.g. PXI or PCI based "digitizers". But, not sure what to expect with "budget-friendly" equipment. Disclaimer: I don't know the AD2 at all. You may be able to solve this problem with a $70 Artix- or Spartan FPGA module and the onboard 1 MSPS/12 bit ADC. The necessary RTL design is relatively straightforward: boilerplate XADC and dump the ADC frame to a UART on end-of-conversion. The UART data rate can go up to about 3 MSPS using FTDI's driver API on the PC side (DLL?) so e.g. 8 bit at 250 ksps should work. I think I tested 6 MBaud once but don't take my word for it and beware of "relatively" straightforward things in FPGA land... Would a 192ksps sound card work?
  24. >> but through the pins when running normally could it be a simple grounding issue?