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Everything posted by xc6lx45

  1. xc6lx45

    related to ' c ' language

    Hi, I think you'll need to add a terminating zero to the string (C string convention), otherwise junk may appear directly afterwards.
  2. And they call it progress... As a tiny bit of good news, inference allows some vendor-independent coding e.g. mapping of multipliers and block ram with the necessary pipeline registers. Well, to be honest, I haven't put it to the test going from X to A or vice versa. But to be honest, I think the hard-macro approach is the only way to go if performance matters. An FPGA is not a "standard cell" ASIC and those two worlds are drifting further apart.
  3. xc6lx45

    GPS Pmod

    I must say I share D@n's opinion here. What I would do is start with a plain serial port. Create a dumb (non-clocked) FPGA design that routes the FTDI chip's UART pins to some GPIOs, and hook up the GPS module. Alternatively, use a standalone FTDI-to-UART module or equivalent. Fire up teraterm (e.g.) on the PC, open the COM port, set the correct baud rate. Check that the GPS module responds as expected. Check that the message format is exactly as you expect it. I suspect this assumption >> it seems, that the given functions from digilents pmodgps.h heather are doing already the right stuff won't hold. What you're trying reminds me of the old joke about a gynecologist retraining as a car mechanic🙂
  4. xc6lx45


    Hi, >> "formal port ja_pin3_io of mode inout cannot be associated with actual port ja_pin3_io of mode out " is this maybe just a typo?
  5. xc6lx45

    Configuring dvi2rgb and rgb2dvi IP blocks on PYNQ board

    OK those critical warnings are related to the VCO, not timing itself. So what I wrote above regarding P&R doesn't apply here.
  6. xc6lx45

    Configuring dvi2rgb and rgb2dvi IP blocks on PYNQ board

    >> that timing requirements may throw a critical warning but the design will work anyway This sets off red flags for me. Just speaking for myself, I wouldn't ever assume this. The problem is that the attempt by P&R to do the impossible may wreak havoc on the rest of the design so it doesn't necessarily "fail soft"
  7. xc6lx45

    Time interval measurement between two pulses

    Hi, generating the frequency is not the problem: The FPGA has PLLs of its own, the board clock frequency does not directly matter for this question. However, designing at 450 MHz will be a specialist job, most likely using a "SERDES" IO block at the input (there is dedicated hardware that eats up e.g. 8 bits at high frequency, and the downstream logic can run at 1/8 the fast rate). I don't think a straightforward counter would work (speed of carry chain). Alternatives might be shift-register based or one-hot FSM (this just from the top of my head). You'll find that FPGA tools require patience under the best of circumstances. Pushing performance to the limit can make design iterations very slow. And, you may have better luck with a Spartan 7 (e.g. CMOD S7 board) than an Artix (e.g. CMOD A7 board). Kintex and Virtex should make this job easier but double-check the required tool licenses. You don't need to own the board to synthesize a test design and get the timing report (e.g. with a 30-day eval version).
  8. xc6lx45

    Nexys2 suddenly stopped working with custom bit files

    Hi, those are just generic things to try. I hope you'll get more specific advice from the official support. is it possible that some obscure options in your ISE project or the constraints file have been changed? I'd try a new copy of the constraints file and download or create a project from scratch. Reinstalling ISE might be another thing to try, just to rule out the possibility that it got damaged. I would get a different USB cable and port, even if the original bitfiles work with the one you've got.
  9. xc6lx45

    FFT / iFFT / RS - Basys3

    I suspect your "ifft" is in reality a conjugated fft Mathematical background (behind this theory and conventional fft-based crosscorrelation): In an FFT-less world, you'd use a so-called "matched filter" as optimal detector that convolves with a time-reversed replica of the known signal (see first line here. Never mind "conjugated" since you have real-valued data). FFT does the convolution. Conjugation in the frequency domain is equivalent to time reversal in the time domain.
  10. xc6lx45

    FFT / iFFT / RS - Basys3

    OK that starts to make more sense. So one channel is reference signal e.g. transmitted signal, one channel the received reflection. Capture both, FFT, multiply (don't forget the conjugate), iFFT. On the bright side, in this specific case you can solve the circularity issues mentioned above with sufficient zero padding on the transmit signal (rule of thumb: Add enough zeros until all reflections have died down to negligible level). This may be easier said than done with a hardware FFT, though... Resolution is limited to the sample rate. If you want to do better, you can interpolate by stealing lines 315..345 here . Needless to say, this calculation needs to be done on a microcontroller or the like. In double precision it's usually accurate to 1 % of a sample. For a reference algorithm, have a look here (this is more complex and somewhat heuristic but has proven itself over the years). With noise-free data this can be accurate to about one nanosample.
  11. xc6lx45

    I Want to make a UI on C#.NET or LabVIEW

    Have a look at Windows Forms. It has some small issues with its dinosaur DNA (e.g. need for pinvoke in a multi-threaded program) but it's mature and industrially proven. Search engines usually give the answer I'm looking for right away. You may also be able to run the code on Linux (mono) with a compatible library, even the same .exe running under Windows and Linux (sounds weird but the runtime takes care of it. The .exe can be really machine independent aka MSIL).
  12. xc6lx45

    FFT / iFFT / RS - Basys3

    Maybe your description of the algorithm is incomplete, but intuitively this does not sound like it would produce any "meaningful" results (e.g. usually IFFT is applied to a complex-valued signal).
  13. xc6lx45

    FFT / iFFT / RS - Basys3

    Hi, if you aren't required to do it on the FPGA, you'll save yourselves a lot of implementation and debugging effort if you do the FFT offline. An Octave script for the job can be found here. It's basically this b = b .* blackmanharris(numel(b)); % calculate spectrum mag = abs(fft(b.')) .^ 2; f_Hz = fd_freqbase(numel(mag)) * rAdc_Hz; % === keep only positive frequencies === mask = (f_Hz >= 0) & (f_Hz < rAdc_Hz / 2); mag = mag(mask); f_Hz = f_Hz(mask); % === convert to dB === mag = 10*log10(mag/max(mag)+eps); h = plot(f_Hz/1e3, mag); %set(h, 'lineWidth', 2); xlabel('f/kHz'); ylabel('dB'); with those two functions function fb = fd_freqbase(n) fb = 0:(n - 1); fb = fb + floor(n / 2); fb = mod(fb, n); fb = fb - floor(n / 2); fb = fb / n; % now [0..0.5[, [-0.5..0[ end function win = blackmanharris(n) a0 = 0.35875; a1 = 0.48829; a2 = 0.14128; a3 = 0.01168; N = n-1; n = [0:N]'; win = a0 - a1.*cos(2.*pi.*n./N) + a2.*cos(4.*pi.*n./N) - a3.*cos(6.*pi.*n./N); end There's many ways to skin a cat... this one has regulatory approval 🙂 This is just about postprocessing. You still need to transfer the data e.g. via a UART. I'd recommend 16 bit binary format. ASCII or hex will be very slow in comparison.
  14. xc6lx45

    Faint 7-seg display LEDs.

    BTW, here is more info on the option regarding pullups: https://forums.xilinx.com/t5/Implementation/Vivado-unused-IOs-behavior/td-p/309557
  15. xc6lx45

    Hello All

    +1 on that ... how about self-driving cars then. At least they are trying really hard not to kill anybody sorry, OT.
  16. xc6lx45

    Hello All

    Hi, random thought: Many physics PhDs end up in finance. Maybe it's about juggling with probability distributions, who knows... FPGA territory starts where the processing latency of a CPU-based trading system becomes a problem. Just a thought...
  17. xc6lx45

    Faint 7-seg display LEDs.

    Hi, the debug core warning is harmless (it's simply not used for a simple RTL-only design). Faintly lit LEDs are fairly common when unused pins are configured to soft pullup (or pulldown). Those pins are routed to one rail via ~10 kOhms internally, The resulting sub-milliampere current isn't enough to light the LED up, but it shows faintly. I can't comment on that specific board. But in general, FPGAs tend to be extremely robust, as long as external voltages are limited to the the IO voltage range (0 V to 3.3 V, typically). Use common sense, but don't worry about the board. It's meant to be used, if it fails it fails and most likely there's not a thing you could have done to change that (other than putting it into a locked closet).
  18. xc6lx45

    Dubts with image processing ZYBO

    ...and "Canny" before "Hough" https://en.wikipedia.org/wiki/Canny_edge_detector
  19. xc6lx45

    Dubts with image processing ZYBO

    Hi, >> I'm a student Why would you use a Zynq? Is this an "external" requirement? It's not necessarily the easiest platform for a simple concept demo. How about a Raspberry Pi with the default camera? It's pretty convenient to work with, and good bang-for-the-buck, too. A Zynq would come in when you need FPGA acceleration, hard real time, a part with very far EOL date, non-consumer (industrial / automotive) hardware or the like. Or a supervisor that demands it... It may be that a simple counting-pixels approach may work. But more often than not, the "simple" tasks are much harder than they look ... students learning this the hard way is a common theme on this forum and others. You might have a look at this (and search in a "computer vision" context), it's a fairly "straightforward" technique for shape recognition, and differently sized coins are a classical example: https://en.wikipedia.org/wiki/Hough_transform "straightforward" in double quotes ... before I try this on FPGA, I better know exactly what I want. Did I mention Raspberry Pi... it has a fairly decent CPU, especially if I make use of the C++ compiler instead of scripting languages (e.g. http://eigen.tuxfamily.org/index.php?title=Main_Page). And this This https://opencv.org/ is one possible starting point.
  20. xc6lx45

    [Zybo Z7] Which Zynq to choose in Vivado

    Hi, most likely it's the slowest speed grade ("C"ommercial). The faster ones are AFAIK only available in "E"xtended (2, 3) or "I"ndustrial (2) temperature range. https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf page 5. As a rule of thumb, the price penalty is fairly substantial, the performance difference is not. Higher speed grades tend to be rare in mass market boards. E.g. see page 27 here: https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf "Minimum clock period" -1=2.5 ns; -2=2.26 ns, -3=2.1 ns but there is more to the topic than just this one number. Of course, a design that is built for -2 or -3 speedgrade would be unreliable on -1 (if the bitstream is even compatible - but I can't recall ever seeing any efuse etc bits that would prevent it in hardware)
  21. I doubt the pin is able to drive a DC motor, which will require take hundreds of milliamperes. You'll need a driver transistor, MOSFET or the like.
  22. xc6lx45

    GPS Pmod

    Hi, >> cold afternoon in the park for one hour not sure if I wanted to take on GPS and FPGA at the same time... I'd probably use a laptop and Teraterm or the like to establish basic functionality via UART. Also, be aware that "cold" starting a GPS module can take a long time. It needs to download the almanac / ephemeris data. 1h seems a lot, but several minutes isn't unusual.
  23. xc6lx45

    OS overhead of the JTAG-USB bits transfer

    Hi, if speed is more important than convenience, you can have a look at my JTAG code here. It works with some of the FTDI-based JTAG adapters, those that follow FTDI's recommended pinout internally. https://github.com/mnentwig/busbridge3/tree/df2f65a8fede13cb5874815da8cf22e81d72123c For example, the final read bit with TMS high is done in line 219 here: https://github.com/mnentwig/busbridge3/blob/df2f65a8fede13cb5874815da8cf22e81d72123c/busBridge3/bb3_lvl3_jtag.cs It collects all events and sends them in block via USB. This should give the fastest possible response time. But the "read" functions cannot immediately return data (since the command sequence is run on hardware only later), they provide a "handle" to return data instead, after the block has been sent to hardware.
  24. xc6lx45

    Prototype for thesis - tarjet selection, help!

    >> embedded system How about a Raspberry PI with wiringPi library, and e.g. some SPI modules? An FPGA is definitely not the tool of choice...
  25. xc6lx45

    Using Adept SDK to handle JTAG on ZC706 board: problems.

    I did a quick experiment: My Artix-based bitstream uploader works just fine with a Zynq if I pad every 6-bit IR word with another 4 zero bits. "0000" for the arm is invalid, which is equivalent to BYPASS (doesn't matter for the uploader since it's not trying to read). Note, I have one reply above awaiting moderation (for unknown reasons, it's strictly technical).